diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 3df13b7fd2..4083721ce9 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -1024,9 +1024,6 @@ class BaseO3DynInst : public ExecContext, public RefCounted
     ThreadContext *tcBase() const override { return thread->getTC(); }
 
   public:
-    /** Returns whether or not the eff. addr. source registers are ready. */
-    bool eaSrcsReady() const;
-
     /** Is this instruction's memory access strictly ordered? */
     bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
     void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; }
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 5e4d3c1759..7bb9dde238 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -202,23 +202,6 @@ BaseO3DynInst<Impl>::markSrcRegReady(RegIndex src_idx)
     markSrcRegReady();
 }
 
-template <class Impl>
-bool
-BaseO3DynInst<Impl>::eaSrcsReady() const
-{
-    // For now I am assuming that src registers 1..n-1 are the ones that the
-    // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
-    // stored)
-
-    for (int i = 1; i < numSrcRegs(); ++i) {
-        if (!regs.readySrcIdx(i))
-            return false;
-    }
-
-    return true;
-}
-
-
 
 template <class Impl>
 void