diff --git a/src/cpu/o3/2bit_local_pred.cc b/src/cpu/2bit_local_pred.cc
similarity index 100%
rename from src/cpu/o3/2bit_local_pred.cc
rename to src/cpu/2bit_local_pred.cc
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 854db9f12d..b14d606b71 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -128,6 +128,13 @@ Source('simple_thread.cc')
 Source('thread_context.cc')
 Source('thread_state.cc')
 
+if 'InOrderCPU' in env['CPU_MODELS'] or 'O3CPU' in env['CPU_MODELS']:
+    Source('btb.cc')
+    Source('tournament_pred.cc')
+    Source('2bit_local_pred.cc')
+    Source('ras.cc')
+    TraceFlag('FreeList')
+
 if env['FULL_SYSTEM']:
     SimObject('IntrControl.py')
 
diff --git a/src/cpu/o3/btb.cc b/src/cpu/btb.cc
similarity index 100%
rename from src/cpu/o3/btb.cc
rename to src/cpu/btb.cc
diff --git a/src/cpu/inorder/SConscript b/src/cpu/inorder/SConscript
index af237a777c..9403aa9140 100644
--- a/src/cpu/inorder/SConscript
+++ b/src/cpu/inorder/SConscript
@@ -35,7 +35,6 @@ if 'InOrderCPU' in env['CPU_MODELS']:
 	SimObject('InOrderTrace.py')
 
 	TraceFlag('ResReqCount')
-	TraceFlag('FreeList')
 	TraceFlag('InOrderStage')
 	TraceFlag('InOrderStall')
 	TraceFlag('InOrderCPU')
@@ -81,10 +80,6 @@ if 'InOrderCPU' in env['CPU_MODELS']:
 	Source('resources/mult_div_unit.cc')
 	Source('resource_pool.cc')
 	Source('reg_dep_map.cc')
-	Source('../o3/btb.cc')
-	Source('../o3/tournament_pred.cc')
-	Source('../o3/2bit_local_pred.cc')
-	Source('../o3/ras.cc')
 	Source('thread_context.cc')
 	Source('cpu.cc')
 
diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
index f05986bf53..6c679e9290 100755
--- a/src/cpu/o3/SConscript
+++ b/src/cpu/o3/SConscript
@@ -33,11 +33,6 @@ import sys
 Import('*')
 
 if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
-    Source('2bit_local_pred.cc')
-    Source('btb.cc')
-    Source('ras.cc')
-    Source('tournament_pred.cc')
-
     TraceFlag('CommitRate')
     TraceFlag('IEW')
     TraceFlag('IQ')
@@ -69,7 +64,6 @@ if 'O3CPU' in env['CPU_MODELS']:
     Source('store_set.cc')
     Source('thread_context.cc')
 
-    TraceFlag('FreeList')
     TraceFlag('LSQ')
     TraceFlag('LSQUnit')
     TraceFlag('MemDepUnit')
diff --git a/src/cpu/o3/ras.cc b/src/cpu/ras.cc
similarity index 100%
rename from src/cpu/o3/ras.cc
rename to src/cpu/ras.cc
diff --git a/src/cpu/o3/tournament_pred.cc b/src/cpu/tournament_pred.cc
similarity index 100%
rename from src/cpu/o3/tournament_pred.cc
rename to src/cpu/tournament_pred.cc