From f36c5d778ba24d41f121b7729628131bd65f053a Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 22 Oct 2021 15:07:34 +0100 Subject: [PATCH] arch-arm: Implement DSB Shareable with a separate class This is an initial step towards making DSB shareable issue a memory operation (generating DVM messages) JIRA: https://gem5.atlassian.net/browse/GEM5-1097 Change-Id: Ia7225acc13008ba1ebdf0b091941f6b494e9d4d6 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56594 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- src/arch/arm/isa/formats/aarch64.isa | 13 +++++++++++-- src/arch/arm/isa/insts/misc64.isa | 21 ++++++++++++++------- 2 files changed, 25 insertions(+), 9 deletions(-) diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 0c6764531b..3c30be6905 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2011-2020 ARM Limited +// Copyright (c) 2011-2021 Arm Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -401,7 +401,16 @@ namespace Aarch64 case 0x2: return new Clrex64(machInst); case 0x4: - return new Dsb64(machInst); + switch (bits(crm, 3, 2)) { + case 0x1: // Non-Shareable + return new Dsb64Local(machInst); + case 0x0: // OuterShareable + case 0x2: // InnerShareable + case 0x3: // FullSystem + return new Dsb64Shareable(machInst); + default: + GEM5_UNREACHABLE; + } case 0x5: return new Dmb64(machInst); case 0x6: diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa index d516c53374..9151b886b8 100644 --- a/src/arch/arm/isa/insts/misc64.isa +++ b/src/arch/arm/isa/insts/misc64.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2011-2013, 2016-2018, 2020 ARM Limited +// Copyright (c) 2011-2013, 2016-2018, 2020-2021 Arm Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -172,12 +172,19 @@ let {{ decoder_output += BasicConstructor64.subst(isbIop) exec_output += BasicExecute.subst(isbIop) - dsbIop = ArmInstObjParams("dsb", "Dsb64", "ArmStaticInst", "", - ['IsReadBarrier', 'IsWriteBarrier', - 'IsSerializeAfter']) - header_output += BasicDeclare.subst(dsbIop) - decoder_output += BasicConstructor64.subst(dsbIop) - exec_output += BasicExecute.subst(dsbIop) + dsbLocalIop = ArmInstObjParams("dsb", "Dsb64Local", "ArmStaticInst", "", + ['IsReadBarrier', 'IsWriteBarrier', + 'IsSerializeAfter']) + header_output += BasicDeclare.subst(dsbLocalIop) + decoder_output += BasicConstructor64.subst(dsbLocalIop) + exec_output += BasicExecute.subst(dsbLocalIop) + + dsbShareableIop = ArmInstObjParams("dsb", "Dsb64Shareable", "ArmStaticInst", "", + ['IsReadBarrier', 'IsWriteBarrier', + 'IsSerializeAfter']) + header_output += BasicDeclare.subst(dsbShareableIop) + decoder_output += BasicConstructor64.subst(dsbShareableIop) + exec_output += BasicExecute.subst(dsbShareableIop) dmbIop = ArmInstObjParams("dmb", "Dmb64", "ArmStaticInst", "", ['IsReadBarrier', 'IsWriteBarrier'])