From f36be791aa8c25cd1531ca9e84f85dcdf2acfb31 Mon Sep 17 00:00:00 2001 From: Matthew Poremba Date: Tue, 13 Feb 2024 16:27:55 -0600 Subject: [PATCH] arch-vega: Expand FLAT subDecode range in main decoder The main decoder for GPU instructions looks at the first 9 bits of a dword to determine either the instruction or a subDecode table with more information for specific instructions types. For flat instructions the first 9 bits currently consist of 6 fixed encoding bits, a reserved bit, and the first two bits of the opcode. Hence to support all opcodes there are four indirections to the flat subDecode table. In MI300 the reserved bit is part of a field to determine memory scope and therefore may be non-zero. This commit adds four addition calls to the subDecode table for the cases where the scope bit is 1. See page 468 (PDF page 478) below: https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/ instruction-set-architectures/ amd-instinct-mi300-cdna3-instruction-set-architecture.pdf Change-Id: Ic3c786f0ca00a758cbe87f42c5e3470576f73a32 --- src/arch/amdgpu/vega/gpu_decoder.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/amdgpu/vega/gpu_decoder.cc b/src/arch/amdgpu/vega/gpu_decoder.cc index 940840719b..2220d820b1 100644 --- a/src/arch/amdgpu/vega/gpu_decoder.cc +++ b/src/arch/amdgpu/vega/gpu_decoder.cc @@ -500,10 +500,10 @@ namespace VegaISA &Decoder::subDecode_OP_FLAT, &Decoder::subDecode_OP_FLAT, &Decoder::subDecode_OP_FLAT, - &Decoder::decode_invalid, - &Decoder::decode_invalid, - &Decoder::decode_invalid, - &Decoder::decode_invalid, + &Decoder::subDecode_OP_FLAT, + &Decoder::subDecode_OP_FLAT, + &Decoder::subDecode_OP_FLAT, + &Decoder::subDecode_OP_FLAT, &Decoder::subDecode_OP_MUBUF, &Decoder::subDecode_OP_MUBUF, &Decoder::subDecode_OP_MUBUF,