diff --git a/src/arch/amdgpu/gcn3/tlb.cc b/src/arch/amdgpu/gcn3/tlb.cc index 4a59c32b63..a6280da04e 100644 --- a/src/arch/amdgpu/gcn3/tlb.cc +++ b/src/arch/amdgpu/gcn3/tlb.cc @@ -512,7 +512,8 @@ namespace X86ISA fatal("GpuTLB doesn't support full-system mode\n"); } else { DPRINTF(GPUTLB, "Handling a TLB miss for address %#x " - "at pc %#x.\n", vaddr, tc->instAddr()); + "at pc %#x.\n", vaddr, + tc->pcState().instAddr()); Process *p = tc->getProcessPtr(); const EmulationPageTable::Entry *pte = diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc b/src/arch/arm/fastmodel/iris/thread_context.cc index 6d76eac7e2..16c8250d94 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.cc +++ b/src/arch/arm/fastmodel/iris/thread_context.cc @@ -590,12 +590,6 @@ ThreadContext::pcState(const PCStateBase &val) call().resource_write(_instId, result, pcRscId, pc); } -Addr -ThreadContext::instAddr() const -{ - return pcState().instAddr(); -} - RegVal ThreadContext::readMiscRegNoEffect(RegIndex misc_reg) const { diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh b/src/arch/arm/fastmodel/iris/thread_context.hh index 620302ff8e..e0a07d1bb4 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.hh +++ b/src/arch/arm/fastmodel/iris/thread_context.hh @@ -351,7 +351,6 @@ class ThreadContext : public gem5::ThreadContext const PCStateBase &pcState() const override; void pcState(const PCStateBase &val) override; - Addr instAddr() const override; RegVal readMiscRegNoEffect(RegIndex misc_reg) const override; RegVal diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc index e462e4fb7f..ecdc602644 100644 --- a/src/arch/arm/kvm/arm_cpu.cc +++ b/src/arch/arm/kvm/arm_cpu.cc @@ -669,8 +669,8 @@ ArmKvmCPU::updateKvmStateCore() setOneReg(ri->id, value); } - DPRINTF(KvmContext, "kvm(PC) := 0x%x\n", tc->instAddr()); - setOneReg(REG_CORE32(usr_regs.ARM_pc), tc->instAddr()); + DPRINTF(KvmContext, "kvm(PC) := 0x%x\n", tc->pcState().instAddr()); + setOneReg(REG_CORE32(usr_regs.ARM_pc), tc->pcState().instAddr()); for (const KvmCoreMiscRegInfo *ri(kvmCoreMiscRegs); ri->idx != NUM_MISCREGS; ++ri) { diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc index 06abd30e49..937b9c61aa 100644 --- a/src/arch/arm/kvm/armv8_cpu.cc +++ b/src/arch/arm/kvm/armv8_cpu.cc @@ -282,8 +282,8 @@ ArmV8KvmCPU::updateKvmState() setOneReg(ri.kvm, value); } - setOneReg(INT_REG(regs.pc), tc->instAddr()); - DPRINTF(KvmContext, " PC := 0x%x\n", tc->instAddr()); + setOneReg(INT_REG(regs.pc), tc->pcState().instAddr()); + DPRINTF(KvmContext, " PC := 0x%x\n", tc->pcState().instAddr()); } void diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc index 703b0ee894..129e76774e 100644 --- a/src/arch/riscv/faults.cc +++ b/src/arch/riscv/faults.cc @@ -141,7 +141,7 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) _cause |= (1L << 63); } tc->setMiscReg(cause, _cause); - tc->setMiscReg(epc, tc->instAddr()); + tc->setMiscReg(epc, tc->pcState().instAddr()); tc->setMiscReg(tval, trap_value()); tc->setMiscReg(MISCREG_PRV, prv); tc->setMiscReg(MISCREG_STATUS, status); diff --git a/src/arch/x86/kvm/x86_cpu.cc b/src/arch/x86/kvm/x86_cpu.cc index 11c017c20e..34ac704ec8 100644 --- a/src/arch/x86/kvm/x86_cpu.cc +++ b/src/arch/x86/kvm/x86_cpu.cc @@ -705,7 +705,7 @@ X86KvmCPU::updateKvmStateRegs() FOREACH_IREG(); #undef APPLY_IREG - regs.rip = tc->instAddr() - tc->readMiscReg(MISCREG_CS_BASE); + regs.rip = tc->pcState().instAddr() - tc->readMiscReg(MISCREG_CS_BASE); /* You might think that setting regs.rflags to the contents * MISCREG_RFLAGS here would suffice. In that case you're diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 9c1a9dae5f..2fc34fbe64 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -383,7 +383,7 @@ TLB::translate(const RequestPtr &req, if (!entry) { DPRINTF(TLB, "Handling a TLB miss for " "address %#x at pc %#x.\n", - vaddr, tc->instAddr()); + vaddr, tc->pcState().instAddr()); if (mode == BaseMMU::Read) { stats.rdMisses++; } else { diff --git a/src/cpu/base.cc b/src/cpu/base.cc index fa793947e3..741ee2d43c 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -255,7 +255,8 @@ BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu) if (secondAddr > addr) size = secondAddr - addr; - req->setVirt(addr, size, 0x0, dataRequestorId(), tc->instAddr()); + req->setVirt(addr, size, 0x0, dataRequestorId(), + tc->pcState().instAddr()); // translate to physical address Fault fault = mmu->translateAtomic(req, tc, BaseMMU::Read); diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 37b19aa235..eb0978f763 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -366,7 +366,6 @@ class CheckerCPU : public BaseCPU, public ExecContext val, thread->pcState()); thread->pcState(val); } - Addr instAddr() { return thread->instAddr(); } ////////////////////////////////////////// RegVal diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index 42b53cdcdb..e8f7b6c9d1 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -230,7 +230,7 @@ Checker::verify(const DynInstPtr &completed_inst) uint64_t fetchOffset = 0; bool fetchDone = false; while (!fetchDone) { - Addr fetch_PC = thread->instAddr(); + Addr fetch_PC = thread->pcState().instAddr(); fetch_PC = (fetch_PC & pc_mask) + fetchOffset; // If not in the middle of a macro instruction @@ -242,7 +242,7 @@ Checker::verify(const DynInstPtr &completed_inst) mem_req->setVirt(fetch_PC, decoder.moreBytesSize(), Request::INST_FETCH, requestorId, - thread->instAddr()); + thread->pcState().instAddr()); fault = mmu->translateFunctional( mem_req, tc, BaseMMU::Execute); @@ -404,10 +404,10 @@ Checker::verify(const DynInstPtr &completed_inst) Addr oldpc; int count = 0; do { - oldpc = thread->instAddr(); + oldpc = thread->pcState().instAddr(); thread->pcEventQueue.service(oldpc, tc); count++; - } while (oldpc != thread->instAddr()); + } while (oldpc != thread->pcState().instAddr()); if (count > 1) { willChangePC = true; set(newPCState, thread->pcState()); @@ -448,7 +448,7 @@ template void Checker::validateInst(const DynInstPtr &inst) { - if (inst->instAddr() != thread->instAddr()) { + if (inst->pcState().instAddr() != thread->pcState().instAddr()) { warn("%lli: PCs do not match! Inst: %s, checker: %s", curTick(), inst->pcState(), thread->pcState()); if (changedPC) { @@ -559,7 +559,8 @@ Checker::validateState() if (updateThisCycle) { // Change this back to warn if divergences end up being false positives panic("%lli: Instruction PC %#x results didn't match up, copying all " - "registers from main CPU", curTick(), unverifiedInst->instAddr()); + "registers from main CPU", curTick(), + unverifiedInst->pcState().instAddr()); // Terribly convoluted way to make sure O3 model does not implode bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC; diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index 81c497318b..115fd1db76 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -340,9 +340,6 @@ class CheckerThreadContext : public ThreadContext return actualTC->pcState(val); } - /** Reads this thread's PC. */ - Addr instAddr() const override { return actualTC->instAddr(); } - RegVal readMiscRegNoEffect(RegIndex misc_reg) const override { diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc index 2b3cb8def6..8de0c560e6 100644 --- a/src/cpu/minor/execute.cc +++ b/src/cpu/minor/execute.cc @@ -851,10 +851,10 @@ Execute::tryPCEvents(ThreadID thread_id) /* Handle PC events on instructions */ Addr oldPC; do { - oldPC = thread->instAddr(); + oldPC = thread->pcState().instAddr(); cpu.threads[thread_id]->pcEventQueue.service(oldPC, thread); num_pc_event_checks++; - } while (oldPC != thread->instAddr()); + } while (oldPC != thread->pcState().instAddr()); if (num_pc_event_checks > 1) { DPRINTF(PCEvent, "Acting on PC Event to PC: %s\n", diff --git a/src/cpu/o3/commit.cc b/src/cpu/o3/commit.cc index c10ced0147..d2011c56d3 100644 --- a/src/cpu/o3/commit.cc +++ b/src/cpu/o3/commit.cc @@ -834,7 +834,7 @@ Commit::commit() "[tid:%i] Squashing due to branch mispred " "PC:%#x [sn:%llu]\n", tid, - fromIEW->mispredictInst[tid]->instAddr(), + fromIEW->mispredictInst[tid]->pcState().instAddr(), fromIEW->squashedSeqNum[tid]); } else { DPRINTF(Commit, diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index 4a3b3350cf..da271ededd 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -311,9 +311,6 @@ class Commit /** Sets the PC of a specific thread. */ void pcState(const PCStateBase &val, ThreadID tid) { set(pc[tid], val); } - /** Returns the PC of a specific thread. */ - Addr instAddr(ThreadID tid) { return pc[tid]->instAddr(); } - private: /** Time buffer interface. */ TimeBuffer *timeBuffer; diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 6e88a28d27..19660b2c51 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1319,12 +1319,6 @@ CPU::pcState(const PCStateBase &val, ThreadID tid) commit.pcState(val, tid); } -Addr -CPU::instAddr(ThreadID tid) -{ - return commit.instAddr(tid); -} - void CPU::squashFromTC(ThreadID tid) { @@ -1356,7 +1350,7 @@ CPU::instDone(ThreadID tid, const DynInstPtr &inst) thread[tid]->threadStats.numOps++; cpuStats.committedOps[tid]++; - probeInstCommit(inst->staticInst, inst->instAddr()); + probeInstCommit(inst->staticInst, inst->pcState().instAddr()); } void @@ -1500,7 +1494,8 @@ CPU::dumpInsts() while (inst_list_it != instList.end()) { cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" "Squashed:%i\n\n", - num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, + num, (*inst_list_it)->pcState().instAddr(), + (*inst_list_it)->threadNumber, (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), (*inst_list_it)->isSquashed()); inst_list_it++; diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 46dbefc16a..ebbfd9a805 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -390,9 +390,6 @@ class CPU : public BaseCPU /** Reads the commit PC state of a specific thread. */ const PCStateBase &pcState(ThreadID tid); - /** Reads the commit PC of a specific thread. */ - Addr instAddr(ThreadID tid); - /** Initiates a squash of all in-flight instructions for a given * thread. The source of the squash is an external update of * state through the TC. diff --git a/src/cpu/o3/dyn_inst.cc b/src/cpu/o3/dyn_inst.cc index 89a7594b79..4769896863 100644 --- a/src/cpu/o3/dyn_inst.cc +++ b/src/cpu/o3/dyn_inst.cc @@ -218,10 +218,10 @@ DynInst::~DynInst() // Print info needed by the pipeline activity viewer. DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n", fetch, - instAddr(), + pcState().instAddr(), pcState().microPC(), seqNum, - staticInst->disassemble(instAddr())); + staticInst->disassemble(pcState().instAddr())); val = (decodeTick == -1) ? 0 : fetch + decodeTick; DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val); diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 7ffb779c4f..f97a525489 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -515,9 +515,6 @@ class DynInst : public ExecContext, public RefCounted const PCStateBase &readPredTarg() { return *predPC; } - /** Returns the predicted PC immediately after the branch. */ - Addr predInstAddr() { return predPC->instAddr(); } - /** Returns whether the instruction was predicted taken or not. */ bool readPredTaken() { return instFlags[PredTaken]; } @@ -904,9 +901,6 @@ class DynInst : public ExecContext, public RefCounted /** Set the PC state of this instruction. */ void pcState(const PCStateBase &val) override { set(pc, val); } - /** Read the PC of this instruction. */ - Addr instAddr() const { return pc->instAddr(); } - bool readPredicate() const override { return instFlags[Predicate]; } void diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc index b9f3e8968c..78999ee46b 100644 --- a/src/cpu/o3/lsq.cc +++ b/src/cpu/o3/lsq.cc @@ -971,7 +971,7 @@ LSQ::SplitDataRequest::initiateTranslation() _mainReq = std::make_shared(base_addr, _size, _flags, _inst->requestorId(), - _inst->instAddr(), _inst->contextId()); + _inst->pcState().instAddr(), _inst->contextId()); _mainReq->setByteEnable(_byteEnable); // Paddr is not used in _mainReq. However, we will accumulate the flags @@ -1086,7 +1086,7 @@ LSQ::LSQRequest::addReq(Addr addr, unsigned size, if (isAnyActiveElement(byte_enable.begin(), byte_enable.end())) { auto req = std::make_shared( addr, size, _flags, _inst->requestorId(), - _inst->instAddr(), _inst->contextId(), + _inst->pcState().instAddr(), _inst->contextId(), std::move(_amo_op)); req->setByteEnable(byte_enable); _reqs.push_back(req); @@ -1173,7 +1173,7 @@ LSQ::SingleDataRequest::buildPackets() DPRINTF(HtmCpu, "HTM %s pc=0x%lx - vaddr=0x%lx - paddr=0x%lx - htmUid=%u\n", isLoad() ? "LD" : "ST", - _inst->instAddr(), + _inst->pcState().instAddr(), _packets.back()->req->hasVaddr() ? _packets.back()->req->getVaddr() : 0lu, _packets.back()->getAddr(), @@ -1203,7 +1203,7 @@ LSQ::SplitDataRequest::buildPackets() _inst->getHtmTransactionUid()); DPRINTF(HtmCpu, "HTM LD.0 pc=0x%lx-vaddr=0x%lx-paddr=0x%lx-htmUid=%u\n", - _inst->instAddr(), + _inst->pcState().instAddr(), _mainPacket->req->hasVaddr() ? _mainPacket->req->getVaddr() : 0lu, _mainPacket->getAddr(), @@ -1237,7 +1237,7 @@ LSQ::SplitDataRequest::buildPackets() "HTM %s.%d pc=0x%lx-vaddr=0x%lx-paddr=0x%lx-htmUid=%u\n", isLoad() ? "LD" : "ST", i+1, - _inst->instAddr(), + _inst->pcState().instAddr(), _packets.back()->req->hasVaddr() ? _packets.back()->req->getVaddr() : 0lu, _packets.back()->getAddr(), diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc index 21bd4697e9..baf09710c5 100644 --- a/src/cpu/o3/lsq_unit.cc +++ b/src/cpu/o3/lsq_unit.cc @@ -1496,7 +1496,7 @@ LSQUnit::read(LSQRequest *request, int load_idx) DPRINTF(HtmCpu, "HTM LD (ST2LDF) " "pc=0x%lx - vaddr=0x%lx - " "paddr=0x%lx - htmUid=%u\n", - load_inst->instAddr(), + load_inst->pcState().instAddr(), data_pkt->req->hasVaddr() ? data_pkt->req->getVaddr() : 0lu, data_pkt->getAddr(), diff --git a/src/cpu/o3/mem_dep_unit.cc b/src/cpu/o3/mem_dep_unit.cc index a35d399095..11a6135b8e 100644 --- a/src/cpu/o3/mem_dep_unit.cc +++ b/src/cpu/o3/mem_dep_unit.cc @@ -220,7 +220,7 @@ MemDepUnit::insert(const DynInstPtr &inst) std::begin(storeBarrierSNs), std::end(storeBarrierSNs)); } else { - InstSeqNum dep = depPred.checkInst(inst->instAddr()); + InstSeqNum dep = depPred.checkInst(inst->pcState().instAddr()); if (dep != 0) producing_stores.push_back(dep); } @@ -286,7 +286,7 @@ MemDepUnit::insert(const DynInstPtr &inst) DPRINTF(MemDepUnit, "Inserting store/atomic PC %s [sn:%lli].\n", inst->pcState(), inst->seqNum); - depPred.insertStore(inst->instAddr(), inst->seqNum, + depPred.insertStore(inst->pcState().instAddr(), inst->seqNum, inst->threadNumber); ++stats.insertedStores; @@ -308,7 +308,7 @@ MemDepUnit::insertNonSpec(const DynInstPtr &inst) DPRINTF(MemDepUnit, "Inserting store/atomic PC %s [sn:%lli].\n", inst->pcState(), inst->seqNum); - depPred.insertStore(inst->instAddr(), inst->seqNum, + depPred.insertStore(inst->pcState().instAddr(), inst->seqNum, inst->threadNumber); ++stats.insertedStores; @@ -572,19 +572,20 @@ MemDepUnit::violation(const DynInstPtr &store_inst, const DynInstPtr &violating_load) { DPRINTF(MemDepUnit, "Passing violating PCs to store sets," - " load: %#x, store: %#x\n", violating_load->instAddr(), - store_inst->instAddr()); + " load: %#x, store: %#x\n", violating_load->pcState().instAddr(), + store_inst->pcState().instAddr()); // Tell the memory dependence unit of the violation. - depPred.violation(store_inst->instAddr(), violating_load->instAddr()); + depPred.violation(store_inst->pcState().instAddr(), + violating_load->pcState().instAddr()); } void MemDepUnit::issue(const DynInstPtr &inst) { DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n", - inst->instAddr(), inst->seqNum); + inst->pcState().instAddr(), inst->seqNum); - depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore()); + depPred.issued(inst->pcState().instAddr(), inst->seqNum, inst->isStore()); } MemDepUnit::MemDepEntryPtr & diff --git a/src/cpu/o3/probe/elastic_trace.cc b/src/cpu/o3/probe/elastic_trace.cc index e93dad3a4a..0a48412571 100644 --- a/src/cpu/o3/probe/elastic_trace.cc +++ b/src/cpu/o3/probe/elastic_trace.cc @@ -418,7 +418,7 @@ ElasticTrace::addDepTraceRecord(const DynInstConstPtr& head_inst, new_record->physAddr = head_inst->physEffAddr; // Currently the tracing does not support split requests. new_record->size = head_inst->effSize; - new_record->pc = head_inst->instAddr(); + new_record->pc = head_inst->pcState().instAddr(); // Assign the timing information stored in the execution info object new_record->executeTick = exec_info_ptr->executeTick; diff --git a/src/cpu/o3/probe/simple_trace.cc b/src/cpu/o3/probe/simple_trace.cc index c44e7abac4..86bc49b156 100644 --- a/src/cpu/o3/probe/simple_trace.cc +++ b/src/cpu/o3/probe/simple_trace.cc @@ -51,16 +51,16 @@ void SimpleTrace::traceCommit(const DynInstConstPtr& dynInst) { DPRINTFR(SimpleTrace, "[%s]: Commit 0x%08x %s.\n", name(), - dynInst->instAddr(), - dynInst->staticInst->disassemble(dynInst->instAddr())); + dynInst->pcState().instAddr(), + dynInst->staticInst->disassemble(dynInst->pcState().instAddr())); } void SimpleTrace::traceFetch(const DynInstConstPtr& dynInst) { DPRINTFR(SimpleTrace, "[%s]: Fetch 0x%08x %s.\n", name(), - dynInst->instAddr(), - dynInst->staticInst->disassemble(dynInst->instAddr())); + dynInst->pcState().instAddr(), + dynInst->staticInst->disassemble(dynInst->pcState().instAddr())); } void diff --git a/src/cpu/o3/rename.cc b/src/cpu/o3/rename.cc index 457b1e902b..a3f8700f46 100644 --- a/src/cpu/o3/rename.cc +++ b/src/cpu/o3/rename.cc @@ -783,7 +783,8 @@ Rename::skidInsert(ThreadID tid) warn("Skidbuffer contents:\n"); for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) { warn("[tid:%i] %s [sn:%llu].\n", tid, - (*it)->staticInst->disassemble(inst->instAddr()), + (*it)->staticInst->disassemble( + inst->pcState().instAddr()), (*it)->seqNum); } panic("Skidbuffer Exceeded Max Size"); diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index ea3ed742ea..03943f4a40 100644 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -288,13 +288,6 @@ class ThreadContext : public gem5::ThreadContext void pcStateNoRecord(const PCStateBase &val) override; - /** Reads this thread's PC. */ - Addr - instAddr() const override - { - return cpu->instAddr(thread->threadId()); - } - /** Reads a miscellaneous register. */ RegVal readMiscRegNoEffect(RegIndex misc_reg) const override diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 549e745754..3e3a94c146 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -122,12 +122,12 @@ BaseSimpleCPU::BaseSimpleCPU(const BaseSimpleCPUParams &p) void BaseSimpleCPU::checkPcEventQueue() { - Addr oldpc, pc = threadInfo[curThread]->thread->instAddr(); + Addr oldpc, pc = threadInfo[curThread]->thread->pcState().instAddr(); do { oldpc = pc; threadInfo[curThread]->thread->pcEventQueue.service( oldpc, threadContexts[curThread]); - pc = threadInfo[curThread]->thread->instAddr(); + pc = threadInfo[curThread]->thread->pcState().instAddr(); } while (oldpc != pc); } @@ -282,7 +282,7 @@ BaseSimpleCPU::setupFetchRequest(const RequestPtr &req) SimpleThread* thread = t_info.thread; auto &decoder = thread->decoder; - Addr instAddr = thread->instAddr(); + Addr instAddr = thread->pcState().instAddr(); Addr fetchPC = (instAddr & decoder.pcMask()) + t_info.fetchOffset; // set up memory request for instruction fetch diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 82e4cc8206..dbbc3ad240 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -456,7 +456,7 @@ TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, SimpleThread* thread = t_info.thread; Fault fault; - const Addr pc = thread->instAddr(); + const Addr pc = thread->pcState().instAddr(); unsigned block_size = cacheLineSize(); BaseMMU::Mode mode = BaseMMU::Read; @@ -530,7 +530,7 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, SimpleThread* thread = t_info.thread; uint8_t *newData = new uint8_t[size]; - const Addr pc = thread->instAddr(); + const Addr pc = thread->pcState().instAddr(); unsigned block_size = cacheLineSize(); BaseMMU::Mode mode = BaseMMU::Write; @@ -594,7 +594,7 @@ TimingSimpleCPU::initiateMemAMO(Addr addr, unsigned size, SimpleThread* thread = t_info.thread; Fault fault; - const Addr pc = thread->instAddr(); + const Addr pc = thread->pcState().instAddr(); unsigned block_size = cacheLineSize(); BaseMMU::Mode mode = BaseMMU::Write; @@ -1219,7 +1219,7 @@ TimingSimpleCPU::initiateHtmCmd(Request::Flags flags) SimpleThread* thread = t_info.thread; const Addr addr = 0x0ul; - const Addr pc = thread->instAddr(); + const Addr pc = thread->pcState().instAddr(); const int size = 8; if (traceData) @@ -1265,7 +1265,7 @@ TimingSimpleCPU::htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, SimpleThread* thread = t_info.thread; const Addr addr = 0x0ul; - const Addr pc = thread->instAddr(); + const Addr pc = thread->pcState().instAddr(); const int size = 8; const Request::Flags flags = Request::PHYSICAL|Request::STRICT_ORDER|Request::HTM_ABORT; diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index ac13d15e51..797ef678c7 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -429,7 +429,6 @@ class SimpleThread : public ThreadState, public ThreadContext set(_pcState, val); } - Addr instAddr() const override { return _pcState->instAddr(); } bool readPredicate() const { return predicate; } void setPredicate(bool val) { predicate = val; } diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 979f70c594..985ffcd80d 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -235,8 +235,6 @@ class ThreadContext : public PCEventScope virtual void pcStateNoRecord(const PCStateBase &val) = 0; - virtual Addr instAddr() const = 0; - virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0; virtual RegVal readMiscReg(RegIndex misc_reg) = 0;