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stdlib, python: Add warning message and clarify binary vs metric units (#1479)

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This PR changes memory and cache sizes in various parts of the gem5
codebase to use binary units (e.g. KiB) instead of metric units (e.g.
kB). This makes the codebase more consistent, as gem5 automatically
converts memory and cache sizes that are in metric units to binary
units.

This PR also adds a warning message to let users know when an
auto-conversion from base 10 to base 2 units occurs.

There were a few places in configs and in the comments of various files
where I didn't change the metric units, as I couldn't figure out where
the parameters with those units were being used.
This commit is contained in:
Bobby R. Bruce
2024-09-17 17:32:27 +00:00
committed by GitHub
parent 6d49130b0b 52c2ecd033
commit f2f86a3e42
106 changed files with 390 additions and 308 deletions
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4
tests/gem5/checkpoint_tests/configs/arm-hello-restore-checkpoint.py
View File

@@ -52,10 +52,10 @@ from gem5.utils.requires import requires
requires(isa_required=ISA.ARM)
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
l1d_size="16kB", l1i_size="16kB", l2_size="256kB"
l1d_size="16KiB", l1i_size="16KiB", l2_size="256KiB"
)
memory = SingleChannelDDR3_1600(size="32MB")
memory = SingleChannelDDR3_1600(size="32MiB")
processor = SimpleProcessor(cpu_type=CPUTypes.ATOMIC, isa=ISA.ARM, num_cores=2)

4
tests/gem5/checkpoint_tests/configs/arm-hello-save-checkpoint.py
View File

@@ -52,10 +52,10 @@ args = parser.parse_args()
requires(isa_required=ISA.ARM)
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
l1d_size="16kB", l1i_size="16kB", l2_size="256kB"
l1d_size="16KiB", l1i_size="16KiB", l2_size="256KiB"
)
memory = SingleChannelDDR3_1600(size="32MB")
memory = SingleChannelDDR3_1600(size="32MiB")
processor = SimpleProcessor(cpu_type=CPUTypes.ATOMIC, isa=ISA.ARM, num_cores=2)
board = SimpleBoard(
clk_freq="3GHz",

2
tests/gem5/checkpoint_tests/configs/power-hello-restore-checkpoint.py
View File

@@ -50,7 +50,7 @@ requires(isa_required=ISA.POWER)
cache_hierarchy = NoCache()
memory = SingleChannelDDR3_1600(size="32MB")
memory = SingleChannelDDR3_1600(size="32MiB")
processor = SimpleProcessor(
cpu_type=CPUTypes.TIMING, isa=ISA.POWER, num_cores=2
)

2
tests/gem5/checkpoint_tests/configs/power-hello-save-checkpoint.py
View File

@@ -58,7 +58,7 @@ requires(isa_required=ISA.POWER)
cache_hierarchy = NoCache()
memory = SingleChannelDDR3_1600(size="32MB")
memory = SingleChannelDDR3_1600(size="32MiB")
processor = SimpleProcessor(
cpu_type=CPUTypes.TIMING, isa=ISA.POWER, num_cores=2
)

2
tests/gem5/checkpoint_tests/configs/sparc-hello-restore-checkpoint.py
View File

@@ -50,7 +50,7 @@ requires(isa_required=ISA.SPARC)
cache_hierarchy = NoCache()
memory = SingleChannelDDR3_1600(size="32MB")
memory = SingleChannelDDR3_1600(size="32MiB")
processor = SimpleProcessor(
cpu_type=CPUTypes.TIMING, isa=ISA.SPARC, num_cores=2
)

2
tests/gem5/checkpoint_tests/configs/sparc-hello-save-checkpoint.py
View File

@@ -58,7 +58,7 @@ requires(isa_required=ISA.SPARC)
cache_hierarchy = NoCache()
memory = SingleChannelDDR3_1600(size="32MB")
memory = SingleChannelDDR3_1600(size="32MiB")
processor = SimpleProcessor(
cpu_type=CPUTypes.TIMING, isa=ISA.SPARC, num_cores=2
)

4
tests/gem5/checkpoint_tests/configs/x86-hello-restore-checkpoint.py
View File

@@ -50,9 +50,9 @@ from gem5.utils.requires import requires
requires(isa_required=ISA.X86)
cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16kB", l1i_size="16kB")
cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16KiB", l1i_size="16KiB")
memory = SingleChannelDDR3_1600(size="32MB")
memory = SingleChannelDDR3_1600(size="32MiB")
processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.X86, num_cores=4)
board = SimpleBoard(
clk_freq="3GHz",

4
tests/gem5/checkpoint_tests/configs/x86-hello-save-checkpoint.py
View File

@@ -58,9 +58,9 @@ parser.add_argument(
args = parser.parse_args()
requires(isa_required=ISA.X86)
cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16kB", l1i_size="16kB")
cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16KiB", l1i_size="16KiB")
memory = SingleChannelDDR3_1600(size="32MB")
memory = SingleChannelDDR3_1600(size="32MiB")
processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.X86, num_cores=4)
board = SimpleBoard(

2
tests/gem5/fs/linux/arm/configs/arm_generic.py
View File

@@ -91,7 +91,7 @@ class LinuxArmSystemBuilder:
self.aarch64_kernel = aarch64_kernel
self.enable_dvm = enable_dvm
self.num_cpus = kwargs.get("num_cpus", 1)
self.mem_size = kwargs.get("mem_size", "256MB")
self.mem_size = kwargs.get("mem_size", "256MiB")
self.use_ruby = kwargs.get("use_ruby", False)
def init_kvm(self, system):

6
tests/gem5/m5threads_test_atomic/caches.py
View File

@@ -77,7 +77,7 @@ class L1ICache(L1Cache):
"""Simple L1 instruction cache with default values"""
# Set the size
size = "32kB"
size = "32KiB"
def __init__(self, opts=None):
super().__init__(opts)
@@ -91,7 +91,7 @@ class L1DCache(L1Cache):
"""Simple L1 data cache with default values"""
# Set the size
size = "32kB"
size = "32KiB"
def __init__(self, opts=None):
super().__init__(opts)
@@ -105,7 +105,7 @@ class L2Cache(PrefetchCache):
"""Simple L2 Cache with default values"""
# Default parameters
size = "256kB"
size = "256KiB"
assoc = 16
tag_latency = 10
data_latency = 10

39
tests/pyunit/util/pyunit_convert_check.py
View File

@@ -277,3 +277,42 @@ class ConvertTestSuite(unittest.TestCase):
self.assertRaises(ValueError, conv, "-1K")
self.assertEqual(conv("32F"), 273.15)
def test_base_10_to_2(self):
conv = convert._base_10_to_2
self.assertEqual(conv("1kB", "B"), "1Ki")
self.assertIsNone(conv("1KiB", "B"))
self.assertEqual(conv("2MB", "B"), "2Mi")
self.assertIsNone(conv("2MiB", "B"))
self.assertEqual(conv("3GB", "B"), "3Gi")
self.assertIsNone(conv("3GiB", "B"))
self.assertEqual(conv("4TB", "B"), "4Ti")
self.assertIsNone(conv("4TiB", "B"))
self.assertEqual(conv("5PB", "B"), "5Pi")
self.assertIsNone(conv("5PiB", "B"))
self.assertEqual(conv("6EB", "B"), "6Ei")
self.assertIsNone(conv("6EiB", "B"))
self.assertEqual(conv("1kB/s", "B/s"), "1Ki")
self.assertIsNone(conv("1KiB/s", "B/s"))
self.assertEqual(conv("2MB/s", "B/s"), "2Mi")
self.assertIsNone(conv("2MiB/s", "B/s"))
self.assertEqual(conv("3GB/s", "B/s"), "3Gi")
self.assertIsNone(conv("3GiB/s", "B/s"))
self.assertEqual(conv("4TB/s", "B/s"), "4Ti")
self.assertIsNone(conv("4TiB/s", "B/s"))
self.assertEqual(conv("5PB/s", "B/s"), "5Pi")
self.assertIsNone(conv("5PiB/s", "B/s"))
self.assertEqual(conv("6EB/s", "B/s"), "6Ei")
self.assertIsNone(conv("6EiB/s", "B/s"))