From f28b51fce08e8e29a23ed38a0657a893613ffc3e Mon Sep 17 00:00:00 2001
From: Derek Christ <christ.derek@gmail.com>
Date: Sun, 26 Nov 2023 07:16:03 +0100
Subject: [PATCH] Enable m5ops and change cache line size to 32

---
 configs/example/gem5_library/arm-baremetal.py | 13 ++++++++++---
 src/mem/dramsys_wrapper.cc                    | 18 ------------------
 src/mem/dramsys_wrapper.hh                    |  1 -
 3 files changed, 10 insertions(+), 22 deletions(-)

diff --git a/configs/example/gem5_library/arm-baremetal.py b/configs/example/gem5_library/arm-baremetal.py
index 3d59f12453..cd341f531e 100644
--- a/configs/example/gem5_library/arm-baremetal.py
+++ b/configs/example/gem5_library/arm-baremetal.py
@@ -8,7 +8,7 @@ from gem5.resources.resource import BinaryResource
 from gem5.simulate.simulator import Simulator
 from m5.objects import VExpress_GEM5_Foundation
 from gem5.components.boards.arm_baremetal_board import ArmBareMetalBoard
-from gem5.components.memory import DRAMSysDDR3_1600
+from gem5.components.memory import DRAMSysHBM2
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.processors.simple_processor import SimpleProcessor
 
@@ -24,7 +24,7 @@ cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
 )
 # cache_hierarchy = NoCache()
 
-memory = DRAMSysDDR3_1600(recordable=True)
+memory = DRAMSysHBM2(recordable=True)
 processor = SimpleProcessor(cpu_type=CPUTypes.O3, num_cores=1, isa=ISA.ARM)
 release = ArmDefaultRelease()
 platform = VExpress_GEM5_Foundation()
@@ -38,12 +38,19 @@ board = ArmBareMetalBoard(
     platform=platform,
 )
 
+# HBM2 requires line size of 32 Bytes
+board.cache_line_size = 32
+
+for core in processor.get_cores():
+    core.core.fetchBufferSize = 32
+
+# Address of memory-mapped m5ops
 board.m5ops_base = 0x10010000
 
 workload = CustomWorkload(
     "set_baremetal_workload",
     {
-        "kernel": BinaryResource("aarch64"),
+        "kernel": BinaryResource("pim-os"),
     },
 )
 board.set_workload(workload)
diff --git a/src/mem/dramsys_wrapper.cc b/src/mem/dramsys_wrapper.cc
index 0b7376bdd8..2decec42a2 100644
--- a/src/mem/dramsys_wrapper.cc
+++ b/src/mem/dramsys_wrapper.cc
@@ -89,24 +89,6 @@ tlm::tlm_sync_enum DRAMSysWrapper::nb_transport_fw(
     // Subtract base address offset
     payload.set_address(payload.get_address() - range.start());
 
-    if (payload.get_address() < 0x4000 && payload.is_write() && phase == tlm::BEGIN_REQ)
-    {
-        char *msg = reinterpret_cast<char*>(payload.get_data_ptr());
-        for (std::size_t i = 0; i < payload.get_data_length(); i++)
-        {
-            if (msg[i] != '\0')
-            {
-                message.push_back(msg[i]);
-            }
-            else
-            {
-                std::cout << message << std::endl;
-                message.clear();
-                break;
-            }
-        }
-    }
-
     return iSocket->nb_transport_fw(payload, phase, fwDelay);
 }
 
diff --git a/src/mem/dramsys_wrapper.hh b/src/mem/dramsys_wrapper.hh
index 11974faaf1..26d552fd2f 100644
--- a/src/mem/dramsys_wrapper.hh
+++ b/src/mem/dramsys_wrapper.hh
@@ -84,7 +84,6 @@ class DRAMSysWrapper : public sc_core::sc_module
     tlm_utils::simple_target_socket<DRAMSysWrapper> tSocket;
 
     std::shared_ptr<::DRAMSys::DRAMSys> dramsys;
-    std::string message;
 
     AddrRange range;
 };