From f1fd8cf7477f230948dab5d8ef14d2043eb09a84 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 7 Jun 2021 15:52:15 +0100
Subject: [PATCH] cpu: Fix MMU port addition from the CheckerCPU

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I596eb74faa2226e49f195c6c178e296f5eca7d37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46621
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/cpu/BaseCPU.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index bd702e2de4..acd1db1e61 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -221,7 +221,7 @@ class BaseCPU(ClockedObject):
             # Checker doesn't need its own tlb caches because it does
             # functional accesses only
             if self.checker != NULL:
-                self._cached_ports += [ ".".join("checker", port) \
+                self._cached_ports += [ "checker." + port
                     for port in ArchMMU.walkerPorts() ]
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None,