diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index bd702e2de4..acd1db1e61 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -221,7 +221,7 @@ class BaseCPU(ClockedObject):
             # Checker doesn't need its own tlb caches because it does
             # functional accesses only
             if self.checker != NULL:
-                self._cached_ports += [ ".".join("checker", port) \
+                self._cached_ports += [ "checker." + port
                     for port in ArchMMU.walkerPorts() ]
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None,