diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index be92761453..8d766471e0 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -87,6 +87,7 @@ class SouthBridge(SimObject):
     ide.BAR3LegacyIO = True
     ide.BAR4 = 1
     ide.Command = 1
+    ide.InterruptLine = 20
 
     def attachIO(self, bus):
         # Route interupt signals
diff --git a/src/dev/x86/pc.cc b/src/dev/x86/pc.cc
index 3dfa50d7ff..5005bd2966 100644
--- a/src/dev/x86/pc.cc
+++ b/src/dev/x86/pc.cc
@@ -127,13 +127,13 @@ Pc::clearConsoleInt()
 void
 Pc::postPciInt(int line)
 {
-    panic("Need implementation\n");
+    southBridge->ioApic->signalInterrupt(line);
 }
 
 void
 Pc::clearPciInt(int line)
 {
-    panic("Need implementation\n");
+    warn_once("Tried to clear PCI interrupt %d\n", line);
 }
 
 Addr