From efe397ca92f6e74c31cc161cff5581a247ec27c1 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Mon, 25 Mar 2024 16:32:31 +0000 Subject: [PATCH] stdlib: Add DTB generation capabilites to AbstractCacheHierarchy Now that we are able to provide a view of the cache hierarchy from the python world, we can start generating DTB entries for caches and more specifically to properly fill the next-level-cache and cache-level properties Change-Id: Iba9ea08fe605f77a353c9e64d62b04b80478b4e2 Signed-off-by: Giacomo Travaglini --- .../abstract_cache_hierarchy.py | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py index a03f0e0c9a..13b4d4f2a2 100644 --- a/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py @@ -43,6 +43,7 @@ from abc import ( from typing import Callable from m5.objects import SubSystem +from m5.util.fdthelper import * from ..boards.abstract_board import AbstractBoard @@ -83,6 +84,21 @@ class CacheNode: self.prev_levels.append(new_node) return new_node + def generate_dtb_entry(self, state, level): + node = FdtNode(f"{self.name}") + node.append(FdtPropertyStrings("compatible", ["cache"])) + node.append(FdtPropertyWords("cache-level", int(level))) + node.append(FdtPropertyWords("cache-size", int(self.cache.size))) + if self.next_level: + node.append( + FdtPropertyWords( + "next-level-cache", state.phandle(self.next_level.cache) + ) + ) + + node.appendPhandle(self.cache) + return node + class AbstractCacheHierarchy(SubSystem): __metaclass__ = ABCMeta @@ -153,3 +169,19 @@ class AbstractCacheHierarchy(SubSystem): visit(node, level) return level + 1 + + def generateDeviceTree(self, state): + dt_entries = [] + + def add_dt_entry(node, level): + # Do not generate a DTB entry for the root node + # as it does not point to a real cache (node.cache = None) + # and for the L1I and L1D caches as their data should be + # part of the CPU node as described by: + # https://devicetree-specification.readthedocs.io/en/stable/devicenodes.html + if node.cache is not None and level != 1: + dt_entries.append(node.generate_dtb_entry(state, level)) + + self.traverse(self._root, add_dt_entry) + + yield from dt_entries