From ef46e4d6a42377bfdb422af80e2671d2ce8c51d5 Mon Sep 17 00:00:00 2001 From: Sandipan Das Date: Sat, 6 Feb 2021 17:19:36 +0530 Subject: [PATCH] arch-power: Refactor compare instructions This changes the base class for integer compare instructions and adds two new classes that are used to distinguish between instructions using different operand types, i.e. register or immediate, and comparison types, i.e. signed or unsigned. The formats have also been updated to make use of the new base classes. Change-Id: Ic6feb803b3a22225d90b8712babd42889b67969d Signed-off-by: Sandipan Das Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40912 Reviewed-by: Boris Shingarov Maintainer: Boris Shingarov Tested-by: kokoro --- src/arch/power/insts/integer.hh | 56 ++++++++++++++++++++++++++ src/arch/power/isa/decoder.isa | 30 +++++--------- src/arch/power/isa/formats/integer.isa | 51 +++++++++++++++++++++++ 3 files changed, 117 insertions(+), 20 deletions(-) diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh index 6433d85a98..6fb797a95d 100644 --- a/src/arch/power/insts/integer.hh +++ b/src/arch/power/insts/integer.hh @@ -406,6 +406,62 @@ class IntDispArithOp : public IntArithOp }; +/** + * Class for integer compare operations. + */ +class IntCompOp : public IntOp +{ + protected: + + bool l; + uint8_t bf; + + /// Constructor + IntCompOp(const char *mnem, MachInst _machInst, OpClass __opClass) + : IntOp(mnem, _machInst, __opClass), + l(machInst.l), + bf(machInst.bf) + { + } +}; + + +/** + * Class for integer immediate compare operations. + */ +class IntImmCompOp : public IntCompOp +{ + protected: + + int32_t si; + + /// Constructor + IntImmCompOp(const char *mnem, MachInst _machInst, OpClass __opClass) + : IntCompOp(mnem, _machInst, __opClass), + si(sext<16>(machInst.si)) + { + } +}; + + +/** + * Class for integer immediate compare logical operations. + */ +class IntImmCompLogicOp : public IntCompOp +{ + protected: + + uint32_t ui; + + /// Constructor + IntImmCompLogicOp(const char *mnem, MachInst _machInst, OpClass __opClass) + : IntCompOp(mnem, _machInst, __opClass), + ui(machInst.ui) + { + } +}; + + /** * Class for integer operations with a shift. */ diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index 3aa973f3b1..221365e362 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -73,19 +73,13 @@ decode PO default Unknown::unknown() { }}, true); } - format IntImmOp { - 10: cmpli({{ - Xer xer = XER; - uint32_t cr = makeCRFieldUnsigned(Ra_uw, ui, xer.so); - CR = insertCRField(CR, BF, cr); - }}); + 10: IntImmCompLogicOp::cmpli({{ + cr = makeCRFieldUnsigned(Ra_uw, ui, xer.so); + }}); - 11: cmpi({{ - Xer xer = XER; - uint32_t cr = makeCRFieldSigned(Ra_sw, si, xer.so); - CR = insertCRField(CR, BF, cr); - }}); - } + 11: IntImmCompOp::cmpi({{ + cr = makeCRFieldSigned(Ra_sw, si, xer.so); + }}); format IntImmArithOp { 12: addic({{ @@ -223,10 +217,8 @@ decode PO default Unknown::unknown() { // nested default cases. 31: decode X_XO { - 0: IntOp::cmp({{ - Xer xer = XER; - uint32_t cr = makeCRFieldSigned(Ra_sw, Rb_sw, xer.so); - CR = insertCRField(CR, BF, cr); + 0: IntCompOp::cmp({{ + cr = makeCRFieldSigned(Ra_sw, Rb_sw, xer.so); }}); format LoadIndexOp { @@ -252,10 +244,8 @@ decode PO default Unknown::unknown() { 28: and({{ Ra = Rs & Rb; }}); } - 32: IntOp::cmpl({{ - Xer xer = XER; - uint32_t cr = makeCRFieldUnsigned(Ra_uw, Rb_uw, xer.so); - CR = insertCRField(CR, BF, cr); + 32: IntCompOp::cmpl({{ + cr = makeCRFieldUnsigned(Ra_uw, Rb_uw, xer.so); }}); 52: LoadIndexOp::lbarx({{ diff --git a/src/arch/power/isa/formats/integer.isa b/src/arch/power/isa/formats/integer.isa index 924198dfcf..04fe79ea5c 100644 --- a/src/arch/power/isa/formats/integer.isa +++ b/src/arch/power/isa/formats/integer.isa @@ -179,6 +179,57 @@ def format IntDispArithOp(code, inst_flags = []) {{ }}; +// Integer compare instructions. +def format IntCompOp(code, inst_flags = []) {{ + + # Add code to setup variables + code = 'GEM5_VAR_USED uint32_t cr = 0;\n' + code + code += 'CR = insertCRField(CR, bf, cr);\n' + + # Add code to access XER + code = readXERCode + code + + # Generate the class + (header_output, decoder_output, decode_block, exec_output) = \ + GenAluOp(name, Name, 'IntCompOp', code, inst_flags, BasicDecode, + BasicConstructor) +}}; + + +// Integer immediate compare instructions. +def format IntImmCompOp(code, inst_flags = []) {{ + + # Add code to setup variables + code = 'GEM5_VAR_USED uint32_t cr = 0;\n' + code + code += 'CR = insertCRField(CR, bf, cr);\n' + + # Add code to access XER + code = readXERCode + code + + # Generate the class + (header_output, decoder_output, decode_block, exec_output) = \ + GenAluOp(name, Name, 'IntImmCompOp', code, inst_flags, BasicDecode, + BasicConstructor) +}}; + + +// Integer immediate compare logical instructions. +def format IntImmCompLogicOp(code, inst_flags = []) {{ + + # Add code to setup variables + code = 'GEM5_VAR_USED uint32_t cr = 0;\n' + code + code += 'CR = insertCRField(CR, bf, cr);\n' + + # Add code to access XER + code = readXERCode + code + + # Generate the class + (header_output, decoder_output, decode_block, exec_output) = \ + GenAluOp(name, Name, 'IntImmCompLogicOp', code, inst_flags, + BasicDecode, BasicConstructor) +}}; + + // Integer instructions that perform logic operations. The result is // always written into Ra. All instructions have 2 versions depending on // whether the Rc bit is set to compute the CR0 code. This is determined