diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 4b9b773c57..12accc3f6d 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -646,6 +646,8 @@ AtomicSimpleCPU::tick()
             return;
         }
 
+        serviceInstCountEvents();
+
         Fault fault = NoFault;
 
         TheISA::PCState pcState = thread->pcState();
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 0a4595ce47..135094fc30 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -302,6 +302,12 @@ BaseSimpleCPU::setupFetchRequest(const RequestPtr &req)
                  instRequestorId(), instAddr);
 }
 
+void
+BaseSimpleCPU::serviceInstCountEvents()
+{
+    SimpleExecContext &t_info = *threadInfo[curThread];
+    t_info.thread->comInstEventQueue.serviceEvents(t_info.numInst);
+}
 
 void
 BaseSimpleCPU::preExecute()
@@ -316,9 +322,6 @@ BaseSimpleCPU::preExecute()
     t_info.setPredicate(true);
     t_info.setMemAccPredicate(true);
 
-    // check for instruction-count-based events
-    thread->comInstEventQueue.serviceEvents(t_info.numInst);
-
     // decode the instruction
     TheISA::PCState pcState = thread->pcState();
 
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 811713864b..cee786d005 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -130,6 +130,7 @@ class BaseSimpleCPU : public BaseCPU
   public:
     void checkForInterrupts();
     void setupFetchRequest(const RequestPtr &req);
+    void serviceInstCountEvents();
     void preExecute();
     void postExecute();
     void advancePC(const Fault &fault);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index ad0e0390dd..76bc1af67b 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -805,6 +805,8 @@ TimingSimpleCPU::advanceInst(const Fault &fault)
     if (tryCompleteDrain())
         return;
 
+    serviceInstCountEvents();
+
     if (_status == BaseSimpleCPU::Running) {
         // kick off fetch of next instruction... callback from icache
         // response will cause that instruction to be executed,