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arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.

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Turn the functions within it into virtual methods on the ISA classes.
Eliminate the implementation in MIPS, which was just copy pasted from
Alpha long ago. Fix some minor style issues in ARM. Remove templating.
Switch from using an "XC" type parameter to using the ThreadContext *
installed in all ISA classes.

The ARM version of these functions actually depend on the ExecContext
delaying writes to MiscRegs to work correctly. More insiduously than
that, they also depend on the conicidental ThreadContext like
availability of certain functions like contextId and getCpuPtr which
come from the class which happened to implement the type passed into XC.

To accomodate that, those functions need both a real ThreadContext, and
another object which is either an ExecContext or a ThreadContext
depending on how the method is called.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1053

Change-Id: I68f95f7283f831776ba76bc5481bfffd18211bc4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50087
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-07-21 04:15:24 -07:00
parent a78fab909a
commit ede1ad4b8c
23 changed files with 345 additions and 842 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/cpu/simple/atomic.cc
View File

@@ -41,7 +41,6 @@
#include "cpu/simple/atomic.hh"
#include "arch/locked_mem.hh"
#include "base/output.hh"
#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
@@ -133,8 +132,8 @@ AtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
wakeup(tid);
}
TheISA::handleLockedSnoop(threadInfo[tid]->thread,
pkt, dcachePort.cacheBlockMask);
threadInfo[tid]->thread->getIsaPtr()->handleLockedSnoop(pkt,
dcachePort.cacheBlockMask);
}
}
}
@@ -298,7 +297,8 @@ AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
pkt->getAddr());
for (auto &t_info : cpu->threadInfo) {
TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
t_info->thread->getIsaPtr()->handleLockedSnoop(pkt,
cacheBlockMask);
}
}
@@ -324,7 +324,8 @@ AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt)
DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
pkt->getAddr());
for (auto &t_info : cpu->threadInfo) {
TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
t_info->thread->getIsaPtr()->handleLockedSnoop(pkt,
cacheBlockMask);
}
}
}
@@ -407,7 +408,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t *data, unsigned size,
assert(!pkt.isError());
if (req->isLLSC()) {
TheISA::handleLockedRead(thread, req);
thread->getIsaPtr()->handleLockedRead(req);
}
}
@@ -482,9 +483,8 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr,
if (req->isLLSC()) {
assert(curr_frag_id == 0);
do_access =
TheISA::handleLockedWrite(thread, req,
dcachePort.cacheBlockMask);
do_access = thread->getIsaPtr()->handleLockedWrite(req,
dcachePort.cacheBlockMask);
} else if (req->isSwap()) {
assert(curr_frag_id == 0);
if (req->isCondSwap()) {

11
src/cpu/simple/timing.cc
View File

@@ -41,7 +41,6 @@
#include "cpu/simple/timing.hh"
#include "arch/locked_mem.hh"
#include "base/compiler.hh"
#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
@@ -276,7 +275,7 @@ TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
// We're about the issues a locked load, so tell the monitor
// to start caring about this address
if (pkt->isRead() && pkt->req->isLLSC()) {
TheISA::handleLockedRead(thread, pkt->req);
thread->getIsaPtr()->handleLockedRead(pkt->req);
}
if (req->isLocalAccess()) {
Cycles delay = req->localAccessor(thread->getTC(), pkt);
@@ -325,7 +324,8 @@ TimingSimpleCPU::sendData(const RequestPtr &req, uint8_t *data, uint64_t *res,
bool do_access = true; // flag to suppress cache access
if (req->isLLSC()) {
do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
do_access = thread->getIsaPtr()->handleLockedWrite(
req, dcachePort.cacheBlockMask);
} else if (req->isCondSwap()) {
assert(res);
req->setExtraData(*res);
@@ -641,7 +641,7 @@ TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
if (getCpuAddrMonitor(tid)->doMonitor(pkt)) {
wakeup(tid);
}
TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt,
threadInfo[tid]->thread->getIsaPtr()->handleLockedSnoop(pkt,
dcachePort.cacheBlockMask);
}
}
@@ -1100,7 +1100,8 @@ TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
// It is not necessary to wake up the processor on all incoming packets
if (pkt->isInvalidate() || pkt->isWrite()) {
for (auto &t_info : cpu->threadInfo) {
TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
t_info->thread->getIsaPtr()->handleLockedSnoop(pkt,
cacheBlockMask);
}
}
}