arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.

Turn the functions within it into virtual methods on the ISA classes.
Eliminate the implementation in MIPS, which was just copy pasted from
Alpha long ago. Fix some minor style issues in ARM. Remove templating.
Switch from using an "XC" type parameter to using the ThreadContext *
installed in all ISA classes.

The ARM version of these functions actually depend on the ExecContext
delaying writes to MiscRegs to work correctly. More insiduously than
that, they also depend on the conicidental ThreadContext like
availability of certain functions like contextId and getCpuPtr which
come from the class which happened to implement the type passed into XC.

To accomodate that, those functions need both a real ThreadContext, and
another object which is either an ExecContext or a ThreadContext
depending on how the method is called.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1053

Change-Id: I68f95f7283f831776ba76bc5481bfffd18211bc4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50087
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/cpu/minor/lsq.cc

@@ -40,7 +40,6 @@
 #include <iomanip>
 #include <sstream>
 
-#include "arch/locked_mem.hh"
 #include "base/compiler.hh"
 #include "base/logging.hh"
 #include "base/trace.hh"
@@ -1137,10 +1136,10 @@ LSQ::tryToSendToTransfers(LSQRequestPtr request)
 
         /* Handle LLSC requests and tests */
         if (is_load) {
-            TheISA::handleLockedRead(&context, request->request);
+            thread.getIsaPtr()->handleLockedRead(&context, request->request);
         } else {
-            do_access = TheISA::handleLockedWrite(&context,
-                request->request, cacheBlockMask);
+            do_access = thread.getIsaPtr()->handleLockedWrite(&context,
+                    request->request, cacheBlockMask);
 
             if (!do_access) {
                 DPRINTF(MinorMem, "Not perfoming a memory "
@@ -1769,8 +1768,8 @@ LSQ::recvTimingSnoopReq(PacketPtr pkt)
 
     if (pkt->isInvalidate() || pkt->isWrite()) {
         for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
-            TheISA::handleLockedSnoop(cpu.getContext(tid), pkt,
-                                      cacheBlockMask);
+            cpu.getContext(tid)->getIsaPtr()->handleLockedSnoop(
+                    pkt, cacheBlockMask);
         }
     }
 }
@@ -1791,8 +1790,8 @@ LSQ::threadSnoop(LSQRequestPtr request)
             }
 
             if (pkt->isInvalidate() || pkt->isWrite()) {
-                TheISA::handleLockedSnoop(cpu.getContext(tid), pkt,
-                                          cacheBlockMask);
+                cpu.getContext(tid)->getIsaPtr()->handleLockedSnoop(pkt,
+                        cacheBlockMask);
             }
         }
     }

src/cpu/o3/lsq_unit.cc

@@ -42,7 +42,6 @@
 #include "cpu/o3/lsq_unit.hh"
 
 #include "arch/generic/debugfaults.hh"
-#include "arch/locked_mem.hh"
 #include "base/str.hh"
 #include "config/the_isa.hh"
 #include "cpu/checker/cpu.hh"
@@ -452,7 +451,7 @@ LSQUnit::checkSnoop(PacketPtr pkt)
         gem5::ThreadContext *tc = cpu->getContext(x);
         bool no_squash = cpu->thread[x]->noSquashFromTC;
         cpu->thread[x]->noSquashFromTC = true;
-        TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask);
+        tc->getIsaPtr()->handleLockedSnoop(pkt, cacheBlockMask);
         cpu->thread[x]->noSquashFromTC = no_squash;
     }
 
@@ -470,8 +469,9 @@ LSQUnit::checkSnoop(PacketPtr pkt)
     // Check that this snoop didn't just invalidate our lock flag
     if (ld_inst->effAddrValid() &&
         req->isCacheBlockHit(invalidate_addr, cacheBlockMask)
-        && ld_inst->memReqFlags & Request::LLSC)
-        TheISA::handleLockedSnoopHit(ld_inst.get());
+        && ld_inst->memReqFlags & Request::LLSC) {
+        ld_inst->tcBase()->getIsaPtr()->handleLockedSnoopHit(ld_inst.get());
+    }
 
     bool force_squash = false;
 
@@ -507,8 +507,10 @@ LSQUnit::checkSnoop(PacketPtr pkt)
                 // Make sure that we don't lose a snoop hitting a LOCKED
                 // address since the LOCK* flags don't get updated until
                 // commit.
-                if (ld_inst->memReqFlags & Request::LLSC)
-                    TheISA::handleLockedSnoopHit(ld_inst.get());
+                if (ld_inst->memReqFlags & Request::LLSC) {
+                    ld_inst->tcBase()->getIsaPtr()->
+                        handleLockedSnoopHit(ld_inst.get());
+                }
 
                 // If a older load checks this and it's true
                 // then we might have missed the snoop
@@ -893,8 +895,8 @@ LSQUnit::writebackStores()
             // misc regs normally updates the result, but this is not
             // the desired behavior when handling store conditionals.
             inst->recordResult(false);
-            bool success = TheISA::handleLockedWrite(inst.get(),
-                    req->request(), cacheBlockMask);
+            bool success = inst->tcBase()->getIsaPtr()->handleLockedWrite(
+                    inst.get(), req->request(), cacheBlockMask);
             inst->recordResult(true);
             req->packetSent();
 
@@ -1359,7 +1361,8 @@ LSQUnit::read(LSQRequest *req, int load_idx)
         // regs normally updates the result, but this is not the
         // desired behavior when handling store conditionals.
         load_inst->recordResult(false);
-        TheISA::handleLockedRead(load_inst.get(), req->mainRequest());
+        load_inst->tcBase()->getIsaPtr()->handleLockedRead(load_inst.get(),
+                req->mainRequest());
         load_inst->recordResult(true);
     }
 

src/cpu/simple/atomic.cc

@@ -41,7 +41,6 @@
 
 #include "cpu/simple/atomic.hh"
 
-#include "arch/locked_mem.hh"
 #include "base/output.hh"
 #include "config/the_isa.hh"
 #include "cpu/exetrace.hh"
@@ -133,8 +132,8 @@ AtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
                 wakeup(tid);
             }
 
-            TheISA::handleLockedSnoop(threadInfo[tid]->thread,
-                                      pkt, dcachePort.cacheBlockMask);
+            threadInfo[tid]->thread->getIsaPtr()->handleLockedSnoop(pkt,
+                    dcachePort.cacheBlockMask);
         }
     }
 }
@@ -298,7 +297,8 @@ AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
         DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
                 pkt->getAddr());
         for (auto &t_info : cpu->threadInfo) {
-            TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
+            t_info->thread->getIsaPtr()->handleLockedSnoop(pkt,
+                    cacheBlockMask);
         }
     }
 
@@ -324,7 +324,8 @@ AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt)
         DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
                 pkt->getAddr());
         for (auto &t_info : cpu->threadInfo) {
-            TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
+            t_info->thread->getIsaPtr()->handleLockedSnoop(pkt,
+                    cacheBlockMask);
         }
     }
 }
@@ -407,7 +408,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t *data, unsigned size,
             assert(!pkt.isError());
 
             if (req->isLLSC()) {
-                TheISA::handleLockedRead(thread, req);
+                thread->getIsaPtr()->handleLockedRead(req);
             }
         }
 
@@ -482,9 +483,8 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr,
 
             if (req->isLLSC()) {
                 assert(curr_frag_id == 0);
-                do_access =
-                    TheISA::handleLockedWrite(thread, req,
-                                              dcachePort.cacheBlockMask);
+                do_access = thread->getIsaPtr()->handleLockedWrite(req,
+                        dcachePort.cacheBlockMask);
             } else if (req->isSwap()) {
                 assert(curr_frag_id == 0);
                 if (req->isCondSwap()) {

src/cpu/simple/timing.cc

@@ -41,7 +41,6 @@
 
 #include "cpu/simple/timing.hh"
 
-#include "arch/locked_mem.hh"
 #include "base/compiler.hh"
 #include "config/the_isa.hh"
 #include "cpu/exetrace.hh"
@@ -276,7 +275,7 @@ TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
     // We're about the issues a locked load, so tell the monitor
     // to start caring about this address
     if (pkt->isRead() && pkt->req->isLLSC()) {
-        TheISA::handleLockedRead(thread, pkt->req);
+        thread->getIsaPtr()->handleLockedRead(pkt->req);
     }
     if (req->isLocalAccess()) {
         Cycles delay = req->localAccessor(thread->getTC(), pkt);
@@ -325,7 +324,8 @@ TimingSimpleCPU::sendData(const RequestPtr &req, uint8_t *data, uint64_t *res,
         bool do_access = true;  // flag to suppress cache access
 
         if (req->isLLSC()) {
-            do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
+            do_access = thread->getIsaPtr()->handleLockedWrite(
+                    req, dcachePort.cacheBlockMask);
         } else if (req->isCondSwap()) {
             assert(res);
             req->setExtraData(*res);
@@ -641,7 +641,7 @@ TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
             if (getCpuAddrMonitor(tid)->doMonitor(pkt)) {
                 wakeup(tid);
             }
-            TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt,
+            threadInfo[tid]->thread->getIsaPtr()->handleLockedSnoop(pkt,
                     dcachePort.cacheBlockMask);
         }
     }
@@ -1100,7 +1100,8 @@ TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
     // It is not necessary to wake up the processor on all incoming packets
     if (pkt->isInvalidate() || pkt->isWrite()) {
         for (auto &t_info : cpu->threadInfo) {
-            TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
+            t_info->thread->getIsaPtr()->handleLockedSnoop(pkt,
+                    cacheBlockMask);
         }
     }
 }