Was having difficulty with merging the cache, reverted to an early version and will add back in the patches to make it work soon.
src/mem/cache/prefetch/tagged_prefetcher_impl.hh:
Trying to merge
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.cc:
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/coherence_protocol.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/base_prefetcher.hh:
src/mem/cache/prefetch/ghb_prefetcher.cc:
src/mem/cache/prefetch/ghb_prefetcher.hh:
src/mem/cache/prefetch/stride_prefetcher.cc:
src/mem/cache/prefetch/stride_prefetcher.hh:
src/mem/cache/prefetch/tagged_prefetcher.hh:
src/mem/cache/tags/base_tags.cc:
src/mem/cache/tags/base_tags.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/repl/gen.cc:
src/mem/cache/tags/repl/gen.hh:
src/mem/cache/tags/repl/repl.cc:
src/mem/cache/tags/repl/repl.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_blk.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
Pulling an early version of the cache into the tree due to merging issues. Will apply patches and push.
--HG--
extra : convert_revision : 3276e5fb9a6272681a1690babf2b586dd0e1f380
This commit is contained in:
Ron Dreslinski
480
src/mem/cache/base_cache.hh
vendored
Normal file
480
src/mem/cache/base_cache.hh
vendored
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@@ -0,0 +1,480 @@
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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*/
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/**
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* @file
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* Declares a basic cache interface BaseCache.
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*/
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#ifndef __BASE_CACHE_HH__
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#define __BASE_CACHE_HH__
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#include <vector>
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#include <string>
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#include <list>
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#include <inttypes.h>
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#include "base/statistics.hh"
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#include "base/trace.hh"
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#include "mem/mem_object.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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#include "mem/request.hh"
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/**
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* Reasons for Caches to be Blocked.
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*/
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enum BlockedCause{
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Blocked_NoMSHRs,
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Blocked_NoTargets,
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Blocked_NoWBBuffers,
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Blocked_Coherence,
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Blocked_Copy,
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NUM_BLOCKED_CAUSES
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};
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/**
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* Reasons for cache to request a bus.
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*/
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enum RequestCause{
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Request_MSHR,
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Request_WB,
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Request_Coherence,
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Request_PF
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};
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/**
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* A basic cache interface. Implements some common functions for speed.
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*/
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class BaseCache : public MemObject
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{
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class CachePort : public Port
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{
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BaseCache *cache;
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public:
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CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
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private:
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virtual bool recvTiming(Packet *pkt);
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virtual Tick recvAtomic(Packet *pkt);
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virtual void recvFunctional(Packet *pkt);
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virtual void recvStatusChange(Status status);
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virtual void getDeviceAddressRanges(AddrRangeList &resp,
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AddrRangeList &snoop);
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virtual int deviceBlockSize();
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void setBlocked();
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void clearBlocked();
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bool blocked;
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bool isCpuSide;
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};
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struct CacheEvent : public Event
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{
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Packet *pkt;
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CachePort *cachePort;
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CacheResponseEvent(Packet *pkt, CachePort *cachePort);
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void process();
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const char *description();
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}
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protected:
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CachePort *cpuSidePort;
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CachePort *memSidePort;
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public:
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virtual Port *getPort(const std::string &if_name);
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private:
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//To be defined in cache_impl.hh not in base class
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virtual bool doTimingAccess(Packet *pkt, MemoryPort *memoryPort, bool isCpuSide);
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virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
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virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
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virtual void recvStatusChange(Port::Status status, bool isCpuSide);
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/**
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* Bit vector of the blocking reasons for the access path.
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* @sa #BlockedCause
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*/
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uint8_t blocked;
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/**
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* Bit vector for the blocking reasons for the snoop path.
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* @sa #BlockedCause
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*/
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uint8_t blockedSnoop;
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/**
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* Bit vector for the outstanding requests for the master interface.
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*/
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uint8_t masterRequests;
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/**
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* Bit vector for the outstanding requests for the slave interface.
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*/
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uint8_t slaveRequests;
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protected:
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/** True if this cache is connected to the CPU. */
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bool topLevelCache;
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/** Stores time the cache blocked for statistics. */
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Tick blockedCycle;
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/** Block size of this cache */
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const int blkSize;
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/** The number of misses to trigger an exit event. */
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Counter missCount;
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public:
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// Statistics
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/**
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* @addtogroup CacheStatistics
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* @{
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*/
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/** Number of hits per thread for each type of command. @sa Packet::Command */
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Stats::Vector<> hits[NUM_MEM_CMDS];
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/** Number of hits for demand accesses. */
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Stats::Formula demandHits;
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/** Number of hit for all accesses. */
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Stats::Formula overallHits;
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/** Number of misses per thread for each type of command. @sa Packet::Command */
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Stats::Vector<> misses[NUM_MEM_CMDS];
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/** Number of misses for demand accesses. */
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Stats::Formula demandMisses;
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/** Number of misses for all accesses. */
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Stats::Formula overallMisses;
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/**
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* Total number of cycles per thread/command spent waiting for a miss.
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* Used to calculate the average miss latency.
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*/
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Stats::Vector<> missLatency[NUM_MEM_CMDS];
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/** Total number of cycles spent waiting for demand misses. */
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Stats::Formula demandMissLatency;
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/** Total number of cycles spent waiting for all misses. */
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Stats::Formula overallMissLatency;
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/** The number of accesses per command and thread. */
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Stats::Formula accesses[NUM_MEM_CMDS];
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/** The number of demand accesses. */
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Stats::Formula demandAccesses;
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/** The number of overall accesses. */
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Stats::Formula overallAccesses;
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/** The miss rate per command and thread. */
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Stats::Formula missRate[NUM_MEM_CMDS];
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/** The miss rate of all demand accesses. */
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Stats::Formula demandMissRate;
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/** The miss rate for all accesses. */
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Stats::Formula overallMissRate;
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/** The average miss latency per command and thread. */
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Stats::Formula avgMissLatency[NUM_MEM_CMDS];
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/** The average miss latency for demand misses. */
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Stats::Formula demandAvgMissLatency;
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/** The average miss latency for all misses. */
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Stats::Formula overallAvgMissLatency;
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/** The total number of cycles blocked for each blocked cause. */
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Stats::Vector<> blocked_cycles;
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/** The number of times this cache blocked for each blocked cause. */
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Stats::Vector<> blocked_causes;
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/** The average number of cycles blocked for each blocked cause. */
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Stats::Formula avg_blocked;
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/** The number of fast writes (WH64) performed. */
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Stats::Scalar<> fastWrites;
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/** The number of cache copies performed. */
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Stats::Scalar<> cacheCopies;
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/**
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* @}
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*/
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/**
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* Register stats for this object.
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*/
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virtual void regStats();
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public:
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class Params
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{
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public:
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/** List of address ranges of this cache. */
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std::vector<Range<Addr> > addrRange;
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/** The hit latency for this cache. */
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int hitLatency;
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/** The block size of this cache. */
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int blkSize;
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/**
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* The maximum number of misses this cache should handle before
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* ending the simulation.
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*/
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Counter maxMisses;
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/**
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* Construct an instance of this parameter class.
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*/
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Params(std::vector<Range<Addr> > addr_range,
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int hit_latency, int _blkSize, Counter max_misses)
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: addrRange(addr_range), hitLatency(hit_latency), blkSize(_blkSize),
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maxMisses(max_misses)
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{
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}
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};
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/**
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* Create and initialize a basic cache object.
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* @param name The name of this cache.
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* @param hier_params Pointer to the HierParams object for this hierarchy
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* of this cache.
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* @param params The parameter object for this BaseCache.
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*/
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BaseCache(const std::string &name, HierParams *hier_params, Params ¶ms)
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: BaseMem(name, hier_params, params.hitLatency, params.addrRange),
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blocked(0), blockedSnoop(0), masterRequests(0), slaveRequests(0),
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topLevelCache(false), blkSize(params.blkSize),
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missCount(params.maxMisses)
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{
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}
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/**
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* Query block size of a cache.
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* @return The block size
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*/
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int getBlockSize() const
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{
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return blkSize;
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}
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/**
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* Returns true if this cache is connect to the CPU.
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* @return True if this is a L1 cache.
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*/
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bool isTopLevel()
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{
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return topLevelCache;
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}
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/**
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* Returns true if the cache is blocked for accesses.
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*/
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bool isBlocked()
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{
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return blocked != 0;
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}
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/**
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* Returns true if the cache is blocked for snoops.
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*/
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bool isBlockedForSnoop()
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{
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return blockedSnoop != 0;
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}
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/**
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* Marks the access path of the cache as blocked for the given cause. This
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* also sets the blocked flag in the slave interface.
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* @param cause The reason for the cache blocking.
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*/
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void setBlocked(BlockedCause cause)
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{
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uint8_t flag = 1 << cause;
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if (blocked == 0) {
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blocked_causes[cause]++;
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blockedCycle = curTick;
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}
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blocked |= flag;
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DPRINTF(Cache,"Blocking for cause %s\n", cause);
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cpuSidePort->setBlocked();
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}
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/**
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* Marks the snoop path of the cache as blocked for the given cause. This
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* also sets the blocked flag in the master interface.
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* @param cause The reason to block the snoop path.
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*/
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void setBlockedForSnoop(BlockedCause cause)
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{
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uint8_t flag = 1 << cause;
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blockedSnoop |= flag;
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memSidePort->setBlocked();
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}
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/**
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* Marks the cache as unblocked for the given cause. This also clears the
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* blocked flags in the appropriate interfaces.
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* @param cause The newly unblocked cause.
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* @warning Calling this function can cause a blocked request on the bus to
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* access the cache. The cache must be in a state to handle that request.
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*/
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void clearBlocked(BlockedCause cause)
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{
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uint8_t flag = 1 << cause;
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blocked &= ~flag;
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blockedSnoop &= ~flag;
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DPRINTF(Cache,"Unblocking for cause %s, causes left=%i\n",
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cause, blocked);
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if (!isBlocked()) {
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blocked_cycles[cause] += curTick - blockedCycle;
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DPRINTF(Cache,"Unblocking from all causes\n");
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cpuSidePort->clearBlocked();
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}
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if (!isBlockedForSnoop()) {
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memSidePort->clearBlocked();
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}
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}
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/**
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* True if the master bus should be requested.
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* @return True if there are outstanding requests for the master bus.
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*/
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bool doMasterRequest()
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{
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return masterRequests != 0;
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}
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/**
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* Request the master bus for the given cause and time.
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* @param cause The reason for the request.
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* @param time The time to make the request.
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*/
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void setMasterRequest(RequestCause cause, Tick time)
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{
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uint8_t flag = 1<<cause;
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masterRequests |= flag;
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assert("Implement\n" && 0);
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// mi->pktuest(time);
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}
|
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|
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/**
|
||||
* Clear the master bus request for the given cause.
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* @param cause The request reason to clear.
|
||||
*/
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||||
void clearMasterRequest(RequestCause cause)
|
||||
{
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||||
uint8_t flag = 1<<cause;
|
||||
masterRequests &= ~flag;
|
||||
}
|
||||
|
||||
/**
|
||||
* Return true if the slave bus should be requested.
|
||||
* @return True if there are outstanding requests for the slave bus.
|
||||
*/
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||||
bool doSlaveRequest()
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||||
{
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||||
return slaveRequests != 0;
|
||||
}
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||||
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||||
/**
|
||||
* Request the slave bus for the given reason and time.
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||||
* @param cause The reason for the request.
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||||
* @param time The time to make the request.
|
||||
*/
|
||||
void setSlaveRequest(RequestCause cause, Tick time)
|
||||
{
|
||||
uint8_t flag = 1<<cause;
|
||||
slaveRequests |= flag;
|
||||
assert("Implement\n" && 0);
|
||||
// si->pktuest(time);
|
||||
}
|
||||
|
||||
/**
|
||||
* Clear the slave bus request for the given reason.
|
||||
* @param cause The request reason to clear.
|
||||
*/
|
||||
void clearSlaveRequest(RequestCause cause)
|
||||
{
|
||||
uint8_t flag = 1<<cause;
|
||||
slaveRequests &= ~flag;
|
||||
}
|
||||
|
||||
/**
|
||||
* Send a response to the slave interface.
|
||||
* @param req The request being responded to.
|
||||
* @param time The time the response is ready.
|
||||
*/
|
||||
void respond(Packet *pkt, Tick time)
|
||||
{
|
||||
assert("Implement\n" && 0);
|
||||
// si->respond(pkt,time);
|
||||
}
|
||||
|
||||
/**
|
||||
* Send a reponse to the slave interface and calculate miss latency.
|
||||
* @param req The request to respond to.
|
||||
* @param time The time the response is ready.
|
||||
*/
|
||||
void respondToMiss(Packet *pkt, Tick time)
|
||||
{
|
||||
if (!pkt->isUncacheable()) {
|
||||
missLatency[pkt->cmd.toIndex()][pkt->thread_num] += time - pkt->time;
|
||||
}
|
||||
assert("Implement\n" && 0);
|
||||
// si->respond(pkt,time);
|
||||
}
|
||||
|
||||
/**
|
||||
* Suppliess the data if cache to cache transfers are enabled.
|
||||
* @param req The bus transaction to fulfill.
|
||||
*/
|
||||
void respondToSnoop(Packet *pkt)
|
||||
{
|
||||
assert("Implement\n" && 0);
|
||||
// mi->respond(pkt,curTick + hitLatency);
|
||||
}
|
||||
|
||||
/**
|
||||
* Notification from master interface that a address range changed. Nothing
|
||||
* to do for a cache.
|
||||
*/
|
||||
void rangeChange() {}
|
||||
};
|
||||
|
||||
#endif //__BASE_CACHE_HH__
|
||||
Reference in New Issue
Block a user