Was having difficulty with merging the cache, reverted to an early version and will add back in the patches to make it work soon.
src/mem/cache/prefetch/tagged_prefetcher_impl.hh:
Trying to merge
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.cc:
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/coherence_protocol.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/base_prefetcher.hh:
src/mem/cache/prefetch/ghb_prefetcher.cc:
src/mem/cache/prefetch/ghb_prefetcher.hh:
src/mem/cache/prefetch/stride_prefetcher.cc:
src/mem/cache/prefetch/stride_prefetcher.hh:
src/mem/cache/prefetch/tagged_prefetcher.hh:
src/mem/cache/tags/base_tags.cc:
src/mem/cache/tags/base_tags.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/repl/gen.cc:
src/mem/cache/tags/repl/gen.hh:
src/mem/cache/tags/repl/repl.cc:
src/mem/cache/tags/repl/repl.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_blk.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
Pulling an early version of the cache into the tree due to merging issues. Will apply patches and push.
--HG--
extra : convert_revision : 3276e5fb9a6272681a1690babf2b586dd0e1f380
This commit is contained in:
Ron Dreslinski
330
src/mem/cache/base_cache.cc
vendored
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330
src/mem/cache/base_cache.cc
vendored
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@@ -0,0 +1,330 @@
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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*/
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/**
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* @file
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* Definition of BaseCache functions.
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*/
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#include "mem/cache/base_cache.hh"
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#include "cpu/smt.hh"
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#include "cpu/base.hh"
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using namespace std;
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BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
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bool _isCpuSide)
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: Port(_name), cache(_cache), isCpuSide(_isCpuSide)
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{
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blocked = false;
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//Start ports at null if more than one is created we should panic
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cpuSidePort = NULL;
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memSidePort = NULL;
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}
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bool
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BaseCache::CachePort::recvStatusChange(Port::Status status)
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{
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cache->recvStatusChange(status, isCpuSide);
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}
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void
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BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp,
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AddrRangeList &snoop)
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{
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cache->getAddressRanges(resp, snoop);
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}
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int
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BaseCache::CachePort::deviceBlockSize()
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{
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return cache->getBlockSize();
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}
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bool
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BaseCache::CachePort::recvTiming(Packet *pkt)
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{
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return cache->doTimingAccess(pkt, this, isCpuSide);
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}
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Tick
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BaseCache::CachePort::recvAtomic(Packet *pkt)
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{
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return cache->doAtomicAccess(pkt, isCpuSide);
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}
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void
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BaseCache::CachePort::recvFunctional(Packet *pkt)
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{
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cache->doFunctionalAccess(pkt, isCpuSide);
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}
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void
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BaseCache::CachePort::setBlocked()
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{
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blocked = true;
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}
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void
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BaseCache::CachePort::clearBlocked()
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{
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blocked = false;
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}
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Port*
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BaseCache::getPort(const std::string &if_name)
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{
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if(if_name == "cpu_side")
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{
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if(cpuSidePort != NULL)
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panic("Already have a cpu side for this cache\n");
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cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
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return cpuSidePort;
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}
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else if(if_name == "mem_side")
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{
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if(memSidePort != NULL)
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panic("Already have a mem side for this cache\n");
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memSidePort = new CachePort(name() + "-mem_side_port", this, false);
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return memSidePort;
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}
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else panic("Port name %s unrecognized\n", if_name);
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}
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void
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BaseCache::regStats()
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{
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using namespace Stats;
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// Hit statistics
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for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
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Packet::Command cmd = (Packet::CommandEnum)access_idx;
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const string &cstr = cmd.toString();
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hits[access_idx]
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.init(maxThreadsPerCPU)
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.name(name() + "." + cstr + "_hits")
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.desc("number of " + cstr + " hits")
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.flags(total | nozero | nonan)
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;
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}
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demandHits
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.name(name() + ".demand_hits")
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.desc("number of demand (read+write) hits")
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.flags(total)
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;
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demandHits = hits[Read] + hits[Write];
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overallHits
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.name(name() + ".overall_hits")
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.desc("number of overall hits")
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.flags(total)
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;
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overallHits = demandHits + hits[Soft_Prefetch] + hits[Hard_Prefetch]
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+ hits[Writeback];
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// Miss statistics
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for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
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Packet::Command cmd = (Packet::CommandEnum)access_idx;
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const string &cstr = cmd.toString();
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misses[access_idx]
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.init(maxThreadsPerCPU)
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.name(name() + "." + cstr + "_misses")
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.desc("number of " + cstr + " misses")
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.flags(total | nozero | nonan)
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;
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}
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demandMisses
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.name(name() + ".demand_misses")
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.desc("number of demand (read+write) misses")
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.flags(total)
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;
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demandMisses = misses[Read] + misses[Write];
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overallMisses
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.name(name() + ".overall_misses")
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.desc("number of overall misses")
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.flags(total)
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;
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overallMisses = demandMisses + misses[Soft_Prefetch] +
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misses[Hard_Prefetch] + misses[Writeback];
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// Miss latency statistics
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for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
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Packet::Command cmd = (Packet::CommandEnum)access_idx;
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const string &cstr = cmd.toString();
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missLatency[access_idx]
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.init(maxThreadsPerCPU)
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.name(name() + "." + cstr + "_miss_latency")
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.desc("number of " + cstr + " miss cycles")
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.flags(total | nozero | nonan)
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;
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}
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demandMissLatency
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.name(name() + ".demand_miss_latency")
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.desc("number of demand (read+write) miss cycles")
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.flags(total)
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;
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demandMissLatency = missLatency[Read] + missLatency[Write];
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overallMissLatency
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.name(name() + ".overall_miss_latency")
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.desc("number of overall miss cycles")
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.flags(total)
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;
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overallMissLatency = demandMissLatency + missLatency[Soft_Prefetch] +
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missLatency[Hard_Prefetch];
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// access formulas
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for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
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Packet::Command cmd = (Packet::CommandEnum)access_idx;
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const string &cstr = cmd.toString();
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accesses[access_idx]
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.name(name() + "." + cstr + "_accesses")
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.desc("number of " + cstr + " accesses(hits+misses)")
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.flags(total | nozero | nonan)
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;
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accesses[access_idx] = hits[access_idx] + misses[access_idx];
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}
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demandAccesses
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.name(name() + ".demand_accesses")
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.desc("number of demand (read+write) accesses")
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.flags(total)
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;
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demandAccesses = demandHits + demandMisses;
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overallAccesses
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.name(name() + ".overall_accesses")
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.desc("number of overall (read+write) accesses")
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.flags(total)
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;
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overallAccesses = overallHits + overallMisses;
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// miss rate formulas
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for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
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Packet::Command cmd = (Packet::CommandEnum)access_idx;
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const string &cstr = cmd.toString();
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missRate[access_idx]
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.name(name() + "." + cstr + "_miss_rate")
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.desc("miss rate for " + cstr + " accesses")
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.flags(total | nozero | nonan)
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;
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missRate[access_idx] = misses[access_idx] / accesses[access_idx];
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}
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demandMissRate
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.name(name() + ".demand_miss_rate")
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.desc("miss rate for demand accesses")
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.flags(total)
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;
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demandMissRate = demandMisses / demandAccesses;
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overallMissRate
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.name(name() + ".overall_miss_rate")
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.desc("miss rate for overall accesses")
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.flags(total)
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;
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overallMissRate = overallMisses / overallAccesses;
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// miss latency formulas
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for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
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Packet::Command cmd = (Packet::CommandEnum)access_idx;
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const string &cstr = cmd.toString();
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avgMissLatency[access_idx]
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.name(name() + "." + cstr + "_avg_miss_latency")
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.desc("average " + cstr + " miss latency")
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.flags(total | nozero | nonan)
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;
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avgMissLatency[access_idx] =
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missLatency[access_idx] / misses[access_idx];
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}
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demandAvgMissLatency
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.name(name() + ".demand_avg_miss_latency")
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.desc("average overall miss latency")
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.flags(total)
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;
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demandAvgMissLatency = demandMissLatency / demandMisses;
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overallAvgMissLatency
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.name(name() + ".overall_avg_miss_latency")
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.desc("average overall miss latency")
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.flags(total)
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;
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overallAvgMissLatency = overallMissLatency / overallMisses;
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blocked_cycles.init(NUM_BLOCKED_CAUSES);
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blocked_cycles
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.name(name() + ".blocked_cycles")
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.desc("number of cycles access was blocked")
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.subname(Blocked_NoMSHRs, "no_mshrs")
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.subname(Blocked_NoTargets, "no_targets")
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;
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blocked_causes.init(NUM_BLOCKED_CAUSES);
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blocked_causes
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.name(name() + ".blocked")
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.desc("number of cycles access was blocked")
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.subname(Blocked_NoMSHRs, "no_mshrs")
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.subname(Blocked_NoTargets, "no_targets")
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;
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avg_blocked
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.name(name() + ".avg_blocked_cycles")
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.desc("average number of cycles each access was blocked")
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.subname(Blocked_NoMSHRs, "no_mshrs")
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.subname(Blocked_NoTargets, "no_targets")
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;
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avg_blocked = blocked_cycles / blocked_causes;
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fastWrites
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.name(name() + ".fast_writes")
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.desc("number of fast writes performed")
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;
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cacheCopies
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.name(name() + ".cache_copies")
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.desc("number of cache copies performed")
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;
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}
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Reference in New Issue
Block a user