get legion/m5 to first tlb miss fault

src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    add sparc error asi
src/arch/sparc/faults.cc:
    put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
    Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
    warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
    add sparc error register code that just does nothing
    fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
    fix implementation of HPSTATE  write
src/cpu/exetrace.cc:
    let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
    add l2 error status register fake devices

--HG--
extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca

src/cpu/exetrace.cc

@@ -57,6 +57,8 @@
 using namespace std;
 using namespace TheISA;
 
+static int diffcount = 0;
+
 namespace Trace {
 SharedData *shared_data = NULL;
 }
@@ -568,7 +570,9 @@ Trace::InstRecord::dump(ostream &outs)
                                     << endl;*/
                             }
                         }
-                        fatal("Differences found between Legion and M5\n");
+                        diffcount++;
+                        if (diffcount > 3)
+                            fatal("Differences found between Legion and M5\n");
                     }
 
                     compared = true;