diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 341346ae15..b0542100bf 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -666,8 +666,10 @@ namespace ArmISA
                 return RegId(CCRegClass, flattenCCIndex(regId.index()));
               case MiscRegClass:
                 return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+              case InvalidRegClass:
+                return RegId();
             }
-            return RegId();
+            panic("Unrecognized register class %d.", regId.classValue());
         }
 
         int
diff --git a/src/cpu/o3/regfile.cc b/src/cpu/o3/regfile.cc
index 4fa79dde8f..3fc7035156 100644
--- a/src/cpu/o3/regfile.cc
+++ b/src/cpu/o3/regfile.cc
@@ -189,6 +189,8 @@ PhysRegFile::getRegIds(RegClassType cls)
         return std::make_pair(ccRegIds.begin(), ccRegIds.end());
       case MiscRegClass:
         return std::make_pair(miscRegIds.begin(), miscRegIds.end());
+      case InvalidRegClass:
+        panic("Tried to get register IDs for the invalid class.");
     }
     /* There is no way to make an empty iterator */
     return std::make_pair(PhysIds::iterator(),
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index ed1683a28d..e368bc400e 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -63,7 +63,8 @@ enum RegClassType
     VecElemClass,
     VecPredRegClass,
     CCRegClass,         ///< Condition-code register
-    MiscRegClass        ///< Control (misc) register
+    MiscRegClass,       ///< Control (misc) register
+    InvalidRegClass = -1
 };
 
 class RegId;
@@ -136,7 +137,7 @@ class RegId
     friend struct std::hash<RegId>;
 
   public:
-    RegId() : RegId(IntRegClass, 0) {}
+    RegId() : RegId(InvalidRegClass, 0) {}
 
     explicit RegId(RegClassType reg_class, RegIndex reg_idx)
         : regClass(reg_class), regIdx(reg_idx), numPinnedWrites(0)
@@ -235,7 +236,7 @@ class PhysRegId : private RegId
     bool pinned;
 
   public:
-    explicit PhysRegId() : RegId(IntRegClass, -1), flatIdx(-1),
+    explicit PhysRegId() : RegId(InvalidRegClass, -1), flatIdx(-1),
                            numPinnedWritesToComplete(0)
     {}