SE/FS: Make SE vs. FS mode a runtime parameter.

tests/configs/inorder-timing.py

@@ -54,4 +54,4 @@ system.system_port = system.membus.port
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)

tests/configs/memtest-ruby.py

@@ -117,7 +117,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency

tests/configs/memtest.py

@@ -86,7 +86,7 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 #root.trace.flags="Cache CachePort MemoryAccess"
 #root.trace.cycle=1

tests/configs/o3-timing-mp-ruby.py

@@ -51,5 +51,5 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'

tests/configs/o3-timing-mp.py

@@ -86,7 +86,7 @@ system.system_port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 #root.trace.flags="Bus Cache"
 #root.trace.flags = "BusAddrRanges"

tests/configs/o3-timing-ruby.py

@@ -43,4 +43,4 @@ system = System(cpu = cpu,
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)

tests/configs/o3-timing.py

@@ -54,4 +54,4 @@ system.system_port = system.membus.port
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)

tests/configs/pc-o3-timing.py

@@ -108,6 +108,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

tests/configs/pc-simple-atomic.py

@@ -110,6 +110,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

tests/configs/pc-simple-timing.py

@@ -110,6 +110,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

tests/configs/realview-o3-dual.py

@@ -94,6 +94,6 @@ for c in cpus:
     c.clock = '2GHz'
 
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

tests/configs/realview-o3.py

@@ -92,6 +92,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

tests/configs/realview-simple-atomic-dual.py

@@ -94,6 +94,6 @@ for c in cpus:
     c.clock = '2GHz'
 
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

tests/configs/realview-simple-atomic.py

@@ -90,6 +90,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

tests/configs/realview-simple-timing-dual.py

@@ -94,6 +94,6 @@ for c in cpus:
     c.clock = '2GHz'
 
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

tests/configs/realview-simple-timing.py

@@ -92,6 +92,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

tests/configs/rubytest-ruby.py

@@ -112,7 +112,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root(full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency

tests/configs/simple-atomic-mp-ruby.py

@@ -52,5 +52,5 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'atomic'

tests/configs/simple-atomic-mp.py

@@ -85,5 +85,5 @@ system.system_port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'atomic'

tests/configs/simple-atomic.py

@@ -37,4 +37,4 @@ system.physmem.port = system.membus.port
 system.cpu.connectAllPorts(system.membus)
 system.cpu.clock = '2GHz'
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)

tests/configs/simple-timing-mp-ruby.py

@@ -95,7 +95,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system=False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency

tests/configs/simple-timing-mp.py

@@ -85,5 +85,5 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'

tests/configs/simple-timing-ruby.py

@@ -91,7 +91,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency

tests/configs/simple-timing.py

@@ -51,4 +51,4 @@ system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system = system)
+root = Root(full_system=False, system = system)

tests/configs/t1000-simple-atomic.py

@@ -36,6 +36,6 @@ system = FSConfig.makeSparcSystem('atomic')
 system.cpu = cpu
 cpu.connectAllPorts(system.membus)
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 
 m5.ticks.setGlobalFrequency('2GHz')

tests/configs/tsunami-inorder.py

@@ -96,6 +96,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

tests/configs/tsunami-o3-dual.py

@@ -95,6 +95,6 @@ for c in cpus:
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

tests/configs/tsunami-o3.py

@@ -93,6 +93,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

tests/configs/tsunami-simple-atomic-dual.py

@@ -93,5 +93,5 @@ for c in cpus:
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')

tests/configs/tsunami-simple-atomic.py

@@ -91,6 +91,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

tests/configs/tsunami-simple-timing-dual.py

@@ -93,7 +93,7 @@ for c in cpus:
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
 

tests/configs/tsunami-simple-timing.py

@@ -93,6 +93,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

tests/configs/twosys-tsunami-simple-atomic.py

@@ -53,6 +53,6 @@ drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
 drive_sys.iobridge.slave = drive_sys.iobus.port
 drive_sys.iobridge.master = drive_sys.membus.port
 
-root = makeDualRoot(test_sys, drive_sys, "ethertrace")
+root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
 
 maxtick = 199999999