arch,cpu,mem: Replace the mmmapped IPR mechanism with local accesses.
The new local access mechanism installs a callback in the request which implements what the mmapped IPR was doing. That avoids having to have stubs in ISAs that don't have mmapped IPRs, avoids having to encode what to do to communicate from the TLB and the mmapped IPR functions, and gets rid of another global ISA interface function and header files. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I772c2ae2ca3830a4486919ce9804560c0f2d596a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23188 Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
@@ -56,6 +56,7 @@
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#include "mem/page_table.hh"
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#include "mem/request.hh"
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#include "sim/process.hh"
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#include "sim/pseudo_inst.hh"
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namespace X86ISA
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{
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@@ -273,8 +274,30 @@ namespace X86ISA
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}
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}
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namespace
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{
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Cycles
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localMiscRegAccess(bool read, MiscRegIndex regNum,
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ThreadContext *tc, PacketPtr pkt)
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{
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if (read) {
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RegVal data = htole(tc->readMiscReg(regNum));
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// Make sure we don't trot off the end of data.
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pkt->setData((uint8_t *)&data);
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} else {
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RegVal data = htole(tc->readMiscRegNoEffect(regNum));
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tc->setMiscReg(regNum, letoh(data));
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}
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return Cycles(1);
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}
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} // anonymous namespace
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Fault
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GpuTLB::translateInt(const RequestPtr &req, ThreadContext *tc)
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GpuTLB::translateInt(bool read, const RequestPtr &req, ThreadContext *tc)
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{
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DPRINTF(GPUTLB, "Addresses references internal memory.\n");
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Addr vaddr = req->getVaddr();
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@@ -283,327 +306,19 @@ namespace X86ISA
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if (prefix == IntAddrPrefixCPUID) {
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panic("CPUID memory space not yet implemented!\n");
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} else if (prefix == IntAddrPrefixMSR) {
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vaddr = vaddr >> 3;
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req->setFlags(Request::MMAPPED_IPR);
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Addr regNum = 0;
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vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
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switch (vaddr & ~IntAddrPrefixMask) {
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case 0x10:
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regNum = MISCREG_TSC;
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break;
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case 0x1B:
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regNum = MISCREG_APIC_BASE;
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break;
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case 0xFE:
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regNum = MISCREG_MTRRCAP;
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break;
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case 0x174:
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regNum = MISCREG_SYSENTER_CS;
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break;
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case 0x175:
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regNum = MISCREG_SYSENTER_ESP;
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break;
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case 0x176:
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regNum = MISCREG_SYSENTER_EIP;
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break;
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case 0x179:
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regNum = MISCREG_MCG_CAP;
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break;
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case 0x17A:
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regNum = MISCREG_MCG_STATUS;
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break;
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case 0x17B:
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regNum = MISCREG_MCG_CTL;
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break;
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case 0x1D9:
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regNum = MISCREG_DEBUG_CTL_MSR;
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break;
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case 0x1DB:
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regNum = MISCREG_LAST_BRANCH_FROM_IP;
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break;
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case 0x1DC:
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regNum = MISCREG_LAST_BRANCH_TO_IP;
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break;
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case 0x1DD:
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regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
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break;
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case 0x1DE:
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regNum = MISCREG_LAST_EXCEPTION_TO_IP;
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break;
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case 0x200:
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regNum = MISCREG_MTRR_PHYS_BASE_0;
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break;
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case 0x201:
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regNum = MISCREG_MTRR_PHYS_MASK_0;
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break;
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case 0x202:
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regNum = MISCREG_MTRR_PHYS_BASE_1;
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break;
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case 0x203:
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regNum = MISCREG_MTRR_PHYS_MASK_1;
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break;
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case 0x204:
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regNum = MISCREG_MTRR_PHYS_BASE_2;
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break;
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case 0x205:
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regNum = MISCREG_MTRR_PHYS_MASK_2;
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break;
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case 0x206:
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regNum = MISCREG_MTRR_PHYS_BASE_3;
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break;
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case 0x207:
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regNum = MISCREG_MTRR_PHYS_MASK_3;
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break;
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case 0x208:
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regNum = MISCREG_MTRR_PHYS_BASE_4;
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break;
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case 0x209:
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regNum = MISCREG_MTRR_PHYS_MASK_4;
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break;
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case 0x20A:
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regNum = MISCREG_MTRR_PHYS_BASE_5;
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break;
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case 0x20B:
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regNum = MISCREG_MTRR_PHYS_MASK_5;
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break;
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case 0x20C:
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regNum = MISCREG_MTRR_PHYS_BASE_6;
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break;
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case 0x20D:
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regNum = MISCREG_MTRR_PHYS_MASK_6;
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break;
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case 0x20E:
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regNum = MISCREG_MTRR_PHYS_BASE_7;
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break;
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case 0x20F:
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regNum = MISCREG_MTRR_PHYS_MASK_7;
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break;
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case 0x250:
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regNum = MISCREG_MTRR_FIX_64K_00000;
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break;
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case 0x258:
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regNum = MISCREG_MTRR_FIX_16K_80000;
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break;
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case 0x259:
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regNum = MISCREG_MTRR_FIX_16K_A0000;
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break;
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case 0x268:
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regNum = MISCREG_MTRR_FIX_4K_C0000;
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break;
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case 0x269:
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regNum = MISCREG_MTRR_FIX_4K_C8000;
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break;
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case 0x26A:
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regNum = MISCREG_MTRR_FIX_4K_D0000;
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break;
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case 0x26B:
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regNum = MISCREG_MTRR_FIX_4K_D8000;
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break;
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case 0x26C:
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regNum = MISCREG_MTRR_FIX_4K_E0000;
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break;
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case 0x26D:
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regNum = MISCREG_MTRR_FIX_4K_E8000;
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break;
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case 0x26E:
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regNum = MISCREG_MTRR_FIX_4K_F0000;
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break;
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case 0x26F:
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regNum = MISCREG_MTRR_FIX_4K_F8000;
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break;
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case 0x277:
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regNum = MISCREG_PAT;
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break;
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case 0x2FF:
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regNum = MISCREG_DEF_TYPE;
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break;
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case 0x400:
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regNum = MISCREG_MC0_CTL;
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break;
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case 0x404:
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regNum = MISCREG_MC1_CTL;
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break;
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case 0x408:
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regNum = MISCREG_MC2_CTL;
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break;
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case 0x40C:
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regNum = MISCREG_MC3_CTL;
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break;
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case 0x410:
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regNum = MISCREG_MC4_CTL;
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break;
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case 0x414:
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regNum = MISCREG_MC5_CTL;
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break;
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case 0x418:
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regNum = MISCREG_MC6_CTL;
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break;
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case 0x41C:
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regNum = MISCREG_MC7_CTL;
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break;
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case 0x401:
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regNum = MISCREG_MC0_STATUS;
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break;
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case 0x405:
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regNum = MISCREG_MC1_STATUS;
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break;
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case 0x409:
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regNum = MISCREG_MC2_STATUS;
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break;
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case 0x40D:
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regNum = MISCREG_MC3_STATUS;
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break;
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case 0x411:
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regNum = MISCREG_MC4_STATUS;
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break;
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case 0x415:
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regNum = MISCREG_MC5_STATUS;
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break;
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case 0x419:
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regNum = MISCREG_MC6_STATUS;
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break;
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case 0x41D:
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regNum = MISCREG_MC7_STATUS;
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break;
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case 0x402:
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regNum = MISCREG_MC0_ADDR;
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break;
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case 0x406:
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regNum = MISCREG_MC1_ADDR;
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break;
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case 0x40A:
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regNum = MISCREG_MC2_ADDR;
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break;
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case 0x40E:
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regNum = MISCREG_MC3_ADDR;
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break;
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case 0x412:
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regNum = MISCREG_MC4_ADDR;
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break;
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case 0x416:
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regNum = MISCREG_MC5_ADDR;
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break;
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case 0x41A:
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regNum = MISCREG_MC6_ADDR;
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break;
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case 0x41E:
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regNum = MISCREG_MC7_ADDR;
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break;
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case 0x403:
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regNum = MISCREG_MC0_MISC;
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break;
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case 0x407:
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regNum = MISCREG_MC1_MISC;
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break;
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case 0x40B:
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regNum = MISCREG_MC2_MISC;
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break;
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case 0x40F:
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regNum = MISCREG_MC3_MISC;
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break;
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case 0x413:
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regNum = MISCREG_MC4_MISC;
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break;
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case 0x417:
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regNum = MISCREG_MC5_MISC;
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break;
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case 0x41B:
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regNum = MISCREG_MC6_MISC;
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break;
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case 0x41F:
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regNum = MISCREG_MC7_MISC;
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break;
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case 0xC0000080:
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regNum = MISCREG_EFER;
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break;
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case 0xC0000081:
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regNum = MISCREG_STAR;
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break;
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case 0xC0000082:
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regNum = MISCREG_LSTAR;
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break;
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case 0xC0000083:
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regNum = MISCREG_CSTAR;
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break;
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case 0xC0000084:
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regNum = MISCREG_SF_MASK;
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break;
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case 0xC0000100:
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regNum = MISCREG_FS_BASE;
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break;
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case 0xC0000101:
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regNum = MISCREG_GS_BASE;
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break;
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case 0xC0000102:
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regNum = MISCREG_KERNEL_GS_BASE;
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break;
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case 0xC0000103:
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regNum = MISCREG_TSC_AUX;
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break;
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case 0xC0010000:
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regNum = MISCREG_PERF_EVT_SEL0;
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break;
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case 0xC0010001:
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regNum = MISCREG_PERF_EVT_SEL1;
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break;
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case 0xC0010002:
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regNum = MISCREG_PERF_EVT_SEL2;
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break;
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case 0xC0010003:
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regNum = MISCREG_PERF_EVT_SEL3;
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break;
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case 0xC0010004:
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regNum = MISCREG_PERF_EVT_CTR0;
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break;
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case 0xC0010005:
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regNum = MISCREG_PERF_EVT_CTR1;
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break;
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case 0xC0010006:
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regNum = MISCREG_PERF_EVT_CTR2;
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break;
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case 0xC0010007:
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regNum = MISCREG_PERF_EVT_CTR3;
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break;
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case 0xC0010010:
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regNum = MISCREG_SYSCFG;
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break;
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case 0xC0010016:
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regNum = MISCREG_IORR_BASE0;
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break;
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case 0xC0010017:
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regNum = MISCREG_IORR_BASE1;
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break;
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case 0xC0010018:
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regNum = MISCREG_IORR_MASK0;
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break;
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case 0xC0010019:
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regNum = MISCREG_IORR_MASK1;
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break;
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case 0xC001001A:
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regNum = MISCREG_TOP_MEM;
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break;
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case 0xC001001D:
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regNum = MISCREG_TOP_MEM2;
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break;
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case 0xC0010114:
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regNum = MISCREG_VM_CR;
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break;
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case 0xC0010115:
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regNum = MISCREG_IGNNE;
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break;
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case 0xC0010116:
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regNum = MISCREG_SMM_CTL;
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break;
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case 0xC0010117:
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regNum = MISCREG_VM_HSAVE_PA;
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break;
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default:
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MiscRegIndex regNum;
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if (!msrAddrToIndex(regNum, vaddr))
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return std::make_shared<GeneralProtection>(0);
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}
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//The index is multiplied by the size of a MiscReg so that
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//any memory dependence calculations will not see these as
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//overlapping.
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req->setPaddr(regNum * sizeof(RegVal));
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req->setLocalAccessor(
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[read,regNum,vaddr](ThreadContext *tc, PacketPtr pkt)
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{
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return localMiscRegAccess(read, regNum, tc, pkt);
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}
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);
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return NoFault;
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} else if (prefix == IntAddrPrefixIO) {
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// TODO If CPL > IOPL or in virtual mode, check the I/O permission
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@@ -613,25 +328,27 @@ namespace X86ISA
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// Make sure the address fits in the expected 16 bit IO address
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// space.
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assert(!(IOPort & ~0xFFFF));
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if (IOPort == 0xCF8 && req->getSize() == 4) {
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req->setFlags(Request::MMAPPED_IPR);
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req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(RegVal));
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req->setLocalAccessor(
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[read](ThreadContext *tc, PacketPtr pkt)
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{
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return localMiscRegAccess(
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read, MISCREG_PCI_CONFIG_ADDRESS, tc, pkt);
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}
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);
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} else if ((IOPort & ~mask(2)) == 0xCFC) {
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req->setFlags(Request::UNCACHEABLE);
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req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
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Addr configAddress =
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tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
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if (bits(configAddress, 31, 31)) {
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req->setPaddr(PhysAddrPrefixPciConfig |
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mbits(configAddress, 30, 2) |
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(IOPort & mask(2)));
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mbits(configAddress, 30, 2) |
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(IOPort & mask(2)));
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} else {
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req->setPaddr(PhysAddrPrefixIO | IOPort);
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}
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} else {
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req->setFlags(Request::UNCACHEABLE);
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req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
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req->setPaddr(PhysAddrPrefixIO | IOPort);
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}
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return NoFault;
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@@ -709,7 +426,7 @@ namespace X86ISA
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// If this is true, we're dealing with a request
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// to a non-memory address space.
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if (seg == SEGMENT_REG_MS) {
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return translateInt(req, tc);
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return translateInt(mode == Read, req, tc);
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}
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delayedResponse = false;
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Reference in New Issue
Block a user