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arch,cpu,mem: Replace the mmmapped IPR mechanism with local accesses.

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The new local access mechanism installs a callback in the request which
implements what the mmapped IPR was doing. That avoids having to have
stubs in ISAs that don't have mmapped IPRs, avoids having to encode
what to do to communicate from the TLB and the mmapped IPR functions,
and gets rid of another global ISA interface function and header files.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I772c2ae2ca3830a4486919ce9804560c0f2d596a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23188
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2019-11-25 19:41:51 -08:00
parent 082ec1a9c7
commit ebd62eff3c
24 changed files with 186 additions and 819 deletions
Download Patch File Download Diff File Expand all files Collapse all files

79
src/arch/arm/mmapped_ipr.hh
View File

@@ -1,79 +0,0 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* Copyright (c) 2007-2008 The Florida State University
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_ARM_MMAPPED_IPR_HH__
#define __ARCH_ARM_MMAPPED_IPR_HH__
/**
* @file
*
* ISA-specific helper functions for memory mapped IPR accesses.
*/
#include "base/types.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/pseudo_inst.hh"
#include "sim/system.hh"
class ThreadContext;
namespace ArmISA
{
inline Cycles
handleIprRead(ThreadContext *tc, Packet *pkt)
{
Addr addr = pkt->getAddr();
auto m5opRange = tc->getSystemPtr()->m5opRange();
if (m5opRange.contains(addr)) {
uint8_t func;
PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
uint64_t ret = PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
pkt->setLE(ret);
}
return Cycles(1);
}
inline Cycles
handleIprWrite(ThreadContext *tc, Packet *pkt)
{
Addr addr = pkt->getAddr();
auto m5opRange = tc->getSystemPtr()->m5opRange();
if (m5opRange.contains(addr)) {
uint8_t func;
PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
}
return Cycles(1);
}
} // namespace ArmISA
#endif

17
src/arch/arm/tlb.cc
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@@ -59,11 +59,13 @@
#include "debug/Checkpoint.hh"
#include "debug/TLB.hh"
#include "debug/TLBVerbose.hh"
#include "mem/packet_access.hh"
#include "mem/page_table.hh"
#include "mem/request.hh"
#include "params/ArmTLB.hh"
#include "sim/full_system.hh"
#include "sim/process.hh"
#include "sim/pseudo_inst.hh"
using namespace std;
using namespace ArmISA;
@@ -133,8 +135,19 @@ TLB::finalizePhysical(const RequestPtr &req,
{
const Addr paddr = req->getPaddr();
if (m5opRange.contains(paddr))
req->setFlags(Request::MMAPPED_IPR);
if (m5opRange.contains(paddr)) {
uint8_t func;
PseudoInst::decodeAddrOffset(paddr - m5opRange.start(), func);
req->setLocalAccessor(
[func, mode](ThreadContext *tc, PacketPtr pkt) -> Cycles
{
uint64_t ret = PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
if (mode == Read)
pkt->setLE(ret);
return Cycles(1);
}
);
}
return NoFault;
}

4
src/arch/arm/tracers/tarmac_parser.cc
View File

@@ -1198,8 +1198,8 @@ TarmacParserRecord::readMemNoEffect(Addr addr, uint8_t *data, unsigned size,
// Now do the access
if (fault == NoFault &&
!req->getFlags().isSet(Request::NO_ACCESS)) {
if (req->isLLSC() || req->isMmappedIpr())
// LLSCs and mem. mapped IPRs are ignored
if (req->isLLSC() || req->isLocalAccess())
// LLSCs and local accesses are ignored
return false;
// the translating proxy will perform the virtual to physical
// translation again