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arch,cpu,mem: Replace the mmmapped IPR mechanism with local accesses.

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The new local access mechanism installs a callback in the request which
implements what the mmapped IPR was doing. That avoids having to have
stubs in ISAs that don't have mmapped IPRs, avoids having to encode
what to do to communicate from the TLB and the mmapped IPR functions,
and gets rid of another global ISA interface function and header files.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I772c2ae2ca3830a4486919ce9804560c0f2d596a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23188
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2019-11-25 19:41:51 -08:00
parent 082ec1a9c7
commit ebd62eff3c
24 changed files with 186 additions and 819 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/arch/SConscript
View File

@@ -63,7 +63,6 @@ env.SwitchingHeaders(
kernel_stats.hh
locked_mem.hh
microcode_rom.hh
mmapped_ipr.hh
process.hh
pseudo_inst.hh
registers.hh

79
src/arch/arm/mmapped_ipr.hh
View File

@@ -1,79 +0,0 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* Copyright (c) 2007-2008 The Florida State University
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_ARM_MMAPPED_IPR_HH__
#define __ARCH_ARM_MMAPPED_IPR_HH__
/**
* @file
*
* ISA-specific helper functions for memory mapped IPR accesses.
*/
#include "base/types.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/pseudo_inst.hh"
#include "sim/system.hh"
class ThreadContext;
namespace ArmISA
{
inline Cycles
handleIprRead(ThreadContext *tc, Packet *pkt)
{
Addr addr = pkt->getAddr();
auto m5opRange = tc->getSystemPtr()->m5opRange();
if (m5opRange.contains(addr)) {
uint8_t func;
PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
uint64_t ret = PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
pkt->setLE(ret);
}
return Cycles(1);
}
inline Cycles
handleIprWrite(ThreadContext *tc, Packet *pkt)
{
Addr addr = pkt->getAddr();
auto m5opRange = tc->getSystemPtr()->m5opRange();
if (m5opRange.contains(addr)) {
uint8_t func;
PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
}
return Cycles(1);
}
} // namespace ArmISA
#endif

17
src/arch/arm/tlb.cc
View File

@@ -59,11 +59,13 @@
#include "debug/Checkpoint.hh"
#include "debug/TLB.hh"
#include "debug/TLBVerbose.hh"
#include "mem/packet_access.hh"
#include "mem/page_table.hh"
#include "mem/request.hh"
#include "params/ArmTLB.hh"
#include "sim/full_system.hh"
#include "sim/process.hh"
#include "sim/pseudo_inst.hh"
using namespace std;
using namespace ArmISA;
@@ -133,8 +135,19 @@ TLB::finalizePhysical(const RequestPtr &req,
{
const Addr paddr = req->getPaddr();
if (m5opRange.contains(paddr))
req->setFlags(Request::MMAPPED_IPR);
if (m5opRange.contains(paddr)) {
uint8_t func;
PseudoInst::decodeAddrOffset(paddr - m5opRange.start(), func);
req->setLocalAccessor(
[func, mode](ThreadContext *tc, PacketPtr pkt) -> Cycles
{
uint64_t ret = PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
if (mode == Read)
pkt->setLE(ret);
return Cycles(1);
}
);
}
return NoFault;
}

4
src/arch/arm/tracers/tarmac_parser.cc
View File

@@ -1198,8 +1198,8 @@ TarmacParserRecord::readMemNoEffect(Addr addr, uint8_t *data, unsigned size,
// Now do the access
if (fault == NoFault &&
!req->getFlags().isSet(Request::NO_ACCESS)) {
if (req->isLLSC() || req->isMmappedIpr())
// LLSCs and mem. mapped IPRs are ignored
if (req->isLLSC() || req->isLocalAccess())
// LLSCs and local accesses are ignored
return false;
// the translating proxy will perform the virtual to physical
// translation again

51
src/arch/mips/mmapped_ipr.hh
View File

@@ -1,51 +0,0 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_MIPS_MMAPPED_IPR_HH__
#define __ARCH_MIPS_MMAPPED_IPR_HH__
/**
* @file
*
* ISA-specific helper functions for memory mapped IPR accesses.
*/
#include "base/types.hh"
class Packet;
class ThreadContext;
namespace MipsISA
{
inline Cycles handleIprRead(ThreadContext *, Packet *) { return Cycles(1); }
inline Cycles handleIprWrite(ThreadContext *, Packet *) { return Cycles(1); }
} // namespace MipsISA
#endif

53
src/arch/power/mmapped_ipr.hh
View File

@@ -1,53 +0,0 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* Copyright (c) 2007-2008 The Florida State University
* Copyright (c) 2009 The University of Edinburgh
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_POWER_MMAPPED_IPR_HH__
#define __ARCH_POWER_MMAPPED_IPR_HH__
/**
* @file
*
* ISA-specific helper functions for memory mapped IPR accesses.
*/
#include "base/types.hh"
class Packet;
class ThreadContext;
namespace PowerISA
{
inline Cycles handleIprRead(ThreadContext *, Packet *) { return Cycles(1); }
inline Cycles handleIprWrite(ThreadContext *, Packet *) { return Cycles(1); }
} // namespace PowerISA
#endif // __ARCH_POWER_MMAPPED_IPR_HH__

51
src/arch/riscv/mmapped_ipr.hh
View File

@@ -1,51 +0,0 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_RISCV_MMAPPED_IPR_HH__
#define __ARCH_RISCV_MMAPPED_IPR_HH__
/**
* @file
*
* ISA-specific helper functions for memory mapped IPR accesses.
*/
#include "base/types.hh"
class Packet;
class ThreadContext;
namespace RiscvISA
{
inline Cycles handleIprRead(ThreadContext *, Packet *) { return Cycles(1); }
inline Cycles handleIprWrite(ThreadContext *, Packet *) { return Cycles(1); }
} // namespace RiscvISA
#endif

60
src/arch/sparc/mmapped_ipr.hh
View File

@@ -1,60 +0,0 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_SPARC_MMAPPED_IPR_HH__
#define __ARCH_SPARC_MMAPPED_IPR_HH__
/**
* @file
*
* ISA-specific helper functions for memory mapped IPR accesses.
*/
#include "arch/sparc/tlb.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
namespace SparcISA
{
inline Cycles
handleIprRead(ThreadContext *xc, Packet *pkt)
{
return dynamic_cast<TLB *>(xc->getDTBPtr())->doMmuRegRead(xc, pkt);
}
inline Cycles
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
return dynamic_cast<TLB *>(xc->getDTBPtr())->doMmuRegWrite(xc, pkt);
}
} // namespace SparcISA
#endif

9
src/arch/sparc/tlb.cc
View File

@@ -825,8 +825,13 @@ handleSparcErrorRegAccess:
regAccessOk:
handleMmuRegAccess:
DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
req->setFlags(Request::MMAPPED_IPR);
DPRINTF(TLB, "TLB: DTB Translating local access\n");
req->setLocalAccessor(
[this,write](ThreadContext *tc, PacketPtr pkt) -> Cycles
{
return write ? doMmuRegWrite(tc, pkt) : doMmuRegRead(tc, pkt);
}
);
req->setPaddr(req->getVaddr());
return NoFault;
};

100
src/arch/x86/mmapped_ipr.hh
View File

@@ -1,100 +0,0 @@
/*
* Copyright (c) 2007-2008 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_X86_MMAPPEDIPR_HH__
#define __ARCH_X86_MMAPPEDIPR_HH__
/**
* @file
*
* ISA-specific helper functions for memory mapped IPR accesses.
*/
#include "arch/x86/pseudo_inst_abi.hh"
#include "arch/x86/regs/misc.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/pseudo_inst.hh"
namespace X86ISA
{
inline Cycles
handleIprRead(ThreadContext *tc, Packet *pkt)
{
Addr addr = pkt->getAddr();
auto m5opRange = tc->getSystemPtr()->m5opRange();
if (m5opRange.contains(addr)) {
uint8_t func;
PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
uint64_t ret = PseudoInst::pseudoInst<X86PseudoInstABI>(tc, func);
pkt->setLE(ret);
} else {
Addr offset = addr & mask(3);
MiscRegIndex index = (MiscRegIndex)(addr / sizeof(RegVal));
RegVal data = htole(tc->readMiscReg(index));
// Make sure we don't trot off the end of data.
assert(offset + pkt->getSize() <= sizeof(RegVal));
pkt->setData(((uint8_t *)&data) + offset);
}
return Cycles(1);
}
inline Cycles
handleIprWrite(ThreadContext *tc, Packet *pkt)
{
Addr addr = pkt->getAddr();
auto m5opRange = tc->getSystemPtr()->m5opRange();
if (m5opRange.contains(addr)) {
uint8_t func;
PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
PseudoInst::pseudoInst<X86PseudoInstABI>(tc, func);
} else {
Addr offset = addr & mask(3);
MiscRegIndex index = (MiscRegIndex)(addr / sizeof(RegVal));
RegVal data = htole(tc->readMiscRegNoEffect(index));
// Make sure we don't trot off the end of data.
assert(offset + pkt->getSize() <= sizeof(RegVal));
pkt->writeData(((uint8_t *)&data) + offset);
tc->setMiscReg(index, letoh(data));
}
return Cycles(1);
}
}
#endif // __ARCH_X86_MMAPPEDIPR_HH__

64
src/arch/x86/tlb.cc
View File

@@ -43,16 +43,19 @@
#include "arch/x86/faults.hh"
#include "arch/x86/insts/microldstop.hh"
#include "arch/x86/pagetable_walker.hh"
#include "arch/x86/pseudo_inst_abi.hh"
#include "arch/x86/regs/misc.hh"
#include "arch/x86/regs/msr.hh"
#include "arch/x86/x86_traits.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/TLB.hh"
#include "mem/packet_access.hh"
#include "mem/page_table.hh"
#include "mem/request.hh"
#include "sim/full_system.hh"
#include "sim/process.hh"
#include "sim/pseudo_inst.hh"
namespace X86ISA {
@@ -166,8 +169,30 @@ TLB::demapPage(Addr va, uint64_t asn)
}
}
namespace
{
Cycles
localMiscRegAccess(bool read, MiscRegIndex regNum,
ThreadContext *tc, PacketPtr pkt)
{
if (read) {
RegVal data = htole(tc->readMiscReg(regNum));
assert(pkt->getSize() <= sizeof(RegVal));
pkt->setData((uint8_t *)&data);
} else {
RegVal data = htole(tc->readMiscRegNoEffect(regNum));
assert(pkt->getSize() <= sizeof(RegVal));
pkt->writeData((uint8_t *)&data);
tc->setMiscReg(regNum, letoh(data));
}
return Cycles(1);
}
} // anonymous namespace
Fault
TLB::translateInt(const RequestPtr &req, ThreadContext *tc)
TLB::translateInt(bool read, RequestPtr req, ThreadContext *tc)
{
DPRINTF(TLB, "Addresses references internal memory.\n");
Addr vaddr = req->getVaddr();
@@ -176,16 +201,18 @@ TLB::translateInt(const RequestPtr &req, ThreadContext *tc)
panic("CPUID memory space not yet implemented!\n");
} else if (prefix == IntAddrPrefixMSR) {
vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
req->setFlags(Request::MMAPPED_IPR);
MiscRegIndex regNum;
if (!msrAddrToIndex(regNum, vaddr))
return std::make_shared<GeneralProtection>(0);
//The index is multiplied by the size of a RegVal so that
//any memory dependence calculations will not see these as
//overlapping.
req->setPaddr((Addr)regNum * sizeof(RegVal));
req->setLocalAccessor(
[read,regNum](ThreadContext *tc, PacketPtr pkt)
{
return localMiscRegAccess(read, regNum, tc, pkt);
}
);
return NoFault;
} else if (prefix == IntAddrPrefixIO) {
// TODO If CPL > IOPL or in virtual mode, check the I/O permission
@@ -196,8 +223,13 @@ TLB::translateInt(const RequestPtr &req, ThreadContext *tc)
// space.
assert(!(IOPort & ~0xFFFF));
if (IOPort == 0xCF8 && req->getSize() == 4) {
req->setFlags(Request::MMAPPED_IPR);
req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(RegVal));
req->setLocalAccessor(
[read](ThreadContext *tc, PacketPtr pkt)
{
return localMiscRegAccess(
read, MISCREG_PCI_CONFIG_ADDRESS, tc, pkt);
}
);
} else if ((IOPort & ~mask(2)) == 0xCFC) {
req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
Addr configAddress =
@@ -227,7 +259,19 @@ TLB::finalizePhysical(const RequestPtr &req,
Addr paddr = req->getPaddr();
if (m5opRange.contains(paddr)) {
req->setFlags(Request::MMAPPED_IPR | Request::STRICT_ORDER);
req->setFlags(Request::STRICT_ORDER);
uint8_t func;
PseudoInst::decodeAddrOffset(paddr - m5opRange.start(), func);
req->setLocalAccessor(
[func, mode](ThreadContext *tc, PacketPtr pkt) -> Cycles
{
uint64_t ret =
PseudoInst::pseudoInst<X86PseudoInstABI>(tc, func);
if (mode == Read)
pkt->setLE(ret);
return Cycles(1);
}
);
} else if (FullSystem) {
// Check for an access to the local APIC
LocalApicBase localApicBase =
@@ -271,7 +315,7 @@ TLB::translate(const RequestPtr &req,
// If this is true, we're dealing with a request to a non-memory address
// space.
if (seg == SEGMENT_REG_MS) {
return translateInt(req, tc);
return translateInt(mode == Read, req, tc);
}
Addr vaddr = req->getVaddr();

2
src/arch/x86/tlb.hh
View File

@@ -106,7 +106,7 @@ namespace X86ISA
Stats::Scalar rdMisses;
Stats::Scalar wrMisses;
Fault translateInt(const RequestPtr &req, ThreadContext *tc);
Fault translateInt(bool read, RequestPtr req, ThreadContext *tc);
Fault translate(const RequestPtr &req, ThreadContext *tc,
Translation *translation, Mode mode,