diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh
index 28b43e6a0c..c9e0ff1a2e 100644
--- a/src/arch/arm/mmu.hh
+++ b/src/arch/arm/mmu.hh
@@ -306,7 +306,7 @@ class MMU : public BaseMMU
         }
 
         if (tlbi_op.stage2Flush()) {
-            flushStage2(tlbi_op.makeStage2());
+            flushStage2(tlbi_op);
         }
     }
 
diff --git a/src/arch/arm/tlbi_op.cc b/src/arch/arm/tlbi_op.cc
index fdb2a160dc..11d9d0a541 100644
--- a/src/arch/arm/tlbi_op.cc
+++ b/src/arch/arm/tlbi_op.cc
@@ -301,14 +301,36 @@ DTLBIMVA::matchEntry(TlbEntry* te, vmid_t vmid) const
 void
 TLBIIPA::operator()(ThreadContext* tc)
 {
-    getMMUPtr(tc)->flushStage2(makeStage2());
+    getMMUPtr(tc)->flushStage2(*this);
 
     CheckerCPU *checker = tc->getCheckerCpuPtr();
     if (checker) {
-        getMMUPtr(checker)->flushStage2(makeStage2());
+        getMMUPtr(checker)->flushStage2(*this);
     }
 }
 
+TlbEntry::Lookup
+TLBIIPA::lookupGen(vmid_t vmid) const
+{
+    TlbEntry::Lookup lookup_data;
+    lookup_data.va = szext<56>(addr);
+    lookup_data.ignoreAsn = true;
+    lookup_data.vmid = vmid;
+    lookup_data.ss = ss;
+    lookup_data.functional = true;
+    lookup_data.targetRegime = targetRegime;
+    lookup_data.mode = BaseMMU::Read;
+    return lookup_data;
+}
+
+bool
+TLBIIPA::matchEntry(TlbEntry* te, vmid_t vmid) const
+{
+    TlbEntry::Lookup lookup_data = lookupGen(vmid);
+
+    return te->match(lookup_data) && (!lastLevel || !te->partial);
+}
+
 bool
 TLBIRMVA::matchEntry(TlbEntry* te, vmid_t vmid) const
 {
@@ -341,5 +363,21 @@ TLBIRMVAA::matchEntry(TlbEntry* te, vmid_t vmid) const
     }
 }
 
+bool
+TLBIRIPA::matchEntry(TlbEntry* te, vmid_t vmid) const
+{
+    TlbEntry::Lookup lookup_data = lookupGen(vmid);
+    lookup_data.size = rangeSize();
+
+    auto addr_match = te->match(lookup_data) && (!lastLevel || !te->partial);
+    if (addr_match) {
+        return tgMap[rangeData.tg] == te->tg &&
+        (resTLBIttl(rangeData.tg, rangeData.ttl) ||
+            rangeData.ttl == te->lookupLevel);
+    } else {
+        return false;
+    }
+}
+
 } // namespace ArmISA
 } // namespace gem5
diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh
index 36bd6c47f5..cb130e8b5e 100644
--- a/src/arch/arm/tlbi_op.hh
+++ b/src/arch/arm/tlbi_op.hh
@@ -135,12 +135,6 @@ class TLBIALL : public TLBIOp
         return currentEL == EL2;
     }
 
-    TLBIALL
-    makeStage2() const
-    {
-        return TLBIALL(targetRegime, ss, attr);
-    }
-
     bool el2Enabled;
     ExceptionLevel currentEL;
 };
@@ -190,13 +184,6 @@ class TLBIALLEL : public TLBIOp
         return targetRegime == TranslationRegime::EL10 ||
                targetRegime == TranslationRegime::EL20;
     }
-
-    TLBIALLEL
-    makeStage2() const
-    {
-        return TLBIALLEL(targetRegime, ss, attr);
-    }
-
 };
 
 /** Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions */
@@ -219,12 +206,6 @@ class TLBIVMALL : public TLBIOp
         return stage2;
     }
 
-    TLBIVMALL
-    makeStage2() const
-    {
-        return TLBIVMALL(targetRegime, ss, false, attr);
-    }
-
     bool el2Enabled;
     bool stage2;
 };
@@ -292,12 +273,6 @@ class TLBIALLN : public TLBIOp
     {
         return targetRegime != TranslationRegime::EL2;
     }
-
-    TLBIALLN
-    makeStage2() const
-    {
-        return TLBIALLN(targetRegime);
-    }
 };
 
 /** TLB Invalidate by VA, All ASID */
@@ -429,6 +404,8 @@ class TLBIRange
 /** TLB Invalidate by Intermediate Physical Address */
 class TLBIIPA : public TLBIOp
 {
+  protected:
+    TlbEntry::Lookup lookupGen(vmid_t vmid) const;
   public:
     TLBIIPA(TranslationRegime _target_regime, SecurityState _ss, Addr _addr,
             bool last_level, Attr _attr=Attr::None)
@@ -437,11 +414,7 @@ class TLBIIPA : public TLBIOp
 
     void operator()(ThreadContext* tc) override;
 
-    bool
-    matchEntry(TlbEntry *entry, vmid_t curr_vmid) const override
-    {
-        panic("This shouldn't be called\n");
-    }
+    bool matchEntry(TlbEntry *entry, vmid_t curr_vmid) const override;
 
     bool
     stage1Flush() const override
@@ -449,13 +422,6 @@ class TLBIIPA : public TLBIOp
         return false;
     }
 
-    /** TLBIIPA is basically a TLBIMVAA for stage2 TLBs */
-    virtual TLBIMVAA
-    makeStage2() const
-    {
-        return TLBIMVAA(targetRegime, ss, addr, lastLevel, attr);
-    }
-
     Addr addr;
     bool lastLevel;
 };
@@ -496,11 +462,7 @@ class TLBIRIPA : public TLBIRange, public TLBIIPA
         TLBIIPA(_target_regime, _ss, startAddress(), last_level, _attr)
     {}
 
-    virtual TLBIMVAA
-    makeStage2() const
-    {
-        return TLBIRMVAA(targetRegime, ss, rangeData, lastLevel, attr);
-    }
+    bool matchEntry(TlbEntry *entry, vmid_t curr_vmid) const override;
 };
 
 } // namespace ArmISA