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cache: Allow main memory to be at disjoint address ranges.

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Ali Saidi
2012-03-09 09:59:25 -05:00
parent cda4c2d280
commit eaa994e7f6
21 changed files with 25 additions and 27 deletions
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2
src/mem/cache/BaseCache.py vendored
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@@ -60,5 +60,5 @@ class BaseCache(MemObject):
prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
cpu_side = SlavePort("Port on side closer to CPU")
mem_side = MasterPort("Port on side closer to MEM")
addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port")
addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port")
system = Param.System(Parent.any, "System we belong to")