cache: Allow main memory to be at disjoint address ranges.

src/mem/cache/BaseCache.py

@@ -60,5 +60,5 @@ class BaseCache(MemObject):
     prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
     cpu_side = SlavePort("Port on side closer to CPU")
     mem_side = MasterPort("Port on side closer to MEM")
-    addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port")
+    addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port")
     system = Param.System(Parent.any, "System we belong to")

src/mem/cache/base.cc

@@ -83,7 +83,7 @@ BaseCache::BaseCache(const Params *p)
       noTargetMSHR(NULL),
       missCount(p->max_miss_count),
       drainEvent(NULL),
-      addrRange(p->addr_range),
+      addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
       system(p->system)
 {
 }

src/mem/cache/base.hh

@@ -269,7 +269,7 @@ class BaseCache : public MemObject
     /**
      * The address range to which the cache responds on the CPU side.
      * Normally this is all possible memory addresses. */
-    Range<Addr> addrRange;
+    AddrRangeList addrRanges;
 
   public:
     /** System we are currently operating in. */
@@ -439,7 +439,7 @@ class BaseCache : public MemObject
     Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
 
 
-    const Range<Addr> &getAddrRange() const { return addrRange; }
+    const AddrRangeList &getAddrRanges() const { return addrRanges; }
 
     MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
     {

src/mem/cache/cache_impl.hh

@@ -1556,9 +1556,7 @@ template<class TagStore>
 AddrRangeList
 Cache<TagStore>::CpuSidePort::getAddrRanges()
 {
-    AddrRangeList ranges;
-    ranges.push_back(cache->getAddrRange());
-    return ranges;
+    return cache->getAddrRanges();
 }
 
 template<class TagStore>