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Update cpus to use the getPort function to use a connector object to connect the I/D cache ports to memory

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configs/test/test.py:
    Update to use new cpu getPort functionality
src/cpu/base.cc:
    Make cpu's a memObject to expose getPort interface
src/cpu/base.hh:
    Make cpu's a memObject to export getPort interface
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Now use the connector via getPort interface
src/mem/cache/base_cache.cc:
    Make sure the cache recognizes all port names

--HG--
extra : convert_revision : dbfefa978ec755bc8aa6f962ae158acf32dafe61
This commit is contained in:
Ron Dreslinski
2006-07-07 15:15:11 -04:00
parent 1ccfdb442f
commit ea11c7bdbe
8 changed files with 43 additions and 19 deletions
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8
src/mem/cache/base_cache.cc vendored
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@@ -144,7 +144,13 @@ BaseCache::getPort(const std::string &if_name, int idx)
cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
return cpuSidePort;
}
if (if_name == "functional")
else if (if_name == "functional")
{
if(cpuSidePort == NULL)
cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
return cpuSidePort;
}
else if (if_name == "cpu_side")
{
if(cpuSidePort == NULL)
cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);