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sim: Make the drain state a global typed enum

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The drain state enum is currently a part of the Drainable
interface. The same state machine will be used by the DrainManager to
identify the global state of the simulator. Make the drain state a
global typed enum to better cater for this usage scenario.
This commit is contained in:
Andreas Sandberg
2015-07-07 09:51:04 +01:00
parent 1dc5e63b88
commit e9c3d59aae
27 changed files with 103 additions and 103 deletions
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4
src/dev/arm/flash_device.cc
View File

@@ -601,10 +601,10 @@ FlashDevice::drain(DrainManager *dm)
if (count) {
DPRINTF(Drain, "Flash device is draining...\n");
setDrainState(Drainable::Draining);
setDrainState(DrainState::Draining);
} else {
DPRINTF(Drain, "Flash device drained\n");
setDrainState(Drainable::Drained);
setDrainState(DrainState::Drained);
}
return count;
}

4
src/dev/arm/ufs_device.cc
View File

@@ -2333,10 +2333,10 @@ UFSHostDevice::drain(DrainManager *dm)
if (count) {
DPRINTF(UFSHostDevice, "UFSDevice is draining...\n");
setDrainState(Drainable::Draining);
setDrainState(DrainState::Draining);
} else {
DPRINTF(UFSHostDevice, "UFSDevice drained\n");
setDrainState(Drainable::Drained);
setDrainState(DrainState::Drained);
}
return count;
}

14
src/dev/copy_engine.cc
View File

@@ -140,12 +140,12 @@ CopyEngine::CopyEngineChannel::recvCommand()
cr.status.dma_transfer_status(0);
nextState = DescriptorFetch;
fetchAddress = cr.descChainAddr;
if (ce->getDrainState() == Drainable::Running)
if (ce->getDrainState() == DrainState::Running)
fetchDescriptor(cr.descChainAddr);
} else if (cr.command.append_dma()) {
if (!busy) {
nextState = AddressFetch;
if (ce->getDrainState() == Drainable::Running)
if (ce->getDrainState() == DrainState::Running)
fetchNextAddr(lastDescriptorAddr);
} else
refreshNext = true;
@@ -635,20 +635,20 @@ CopyEngine::CopyEngineChannel::fetchAddrComplete()
bool
CopyEngine::CopyEngineChannel::inDrain()
{
if (ce->getDrainState() == Drainable::Draining) {
if (ce->getDrainState() == DrainState::Draining) {
DPRINTF(Drain, "CopyEngine done draining, processing drain event\n");
assert(drainManager);
drainManager->signalDrainDone();
drainManager = NULL;
}
return ce->getDrainState() != Drainable::Running;
return ce->getDrainState() != DrainState::Running;
}
unsigned int
CopyEngine::CopyEngineChannel::drain(DrainManager *dm)
{
if (nextState == Idle || ce->getDrainState() != Drainable::Running)
if (nextState == Idle || ce->getDrainState() != DrainState::Running)
return 0;
unsigned int count = 1;
count += cePort.drain(dm);
@@ -667,9 +667,9 @@ CopyEngine::drain(DrainManager *dm)
count += chan[x]->drain(dm);
if (count)
setDrainState(Draining);
setDrainState(DrainState::Draining);
else
setDrainState(Drained);
setDrainState(DrainState::Drained);
DPRINTF(Drain, "CopyEngine not drained\n");
return count;

4
src/dev/dma_device.cc
View File

@@ -130,9 +130,9 @@ DmaDevice::drain(DrainManager *dm)
{
unsigned int count = pioPort.drain(dm) + dmaPort.drain(dm);
if (count)
setDrainState(Drainable::Draining);
setDrainState(DrainState::Draining);
else
setDrainState(Drainable::Drained);
setDrainState(DrainState::Drained);
return count;
}

14
src/dev/i8254xGBe.cc
View File

@@ -586,7 +586,7 @@ IGbE::write(PacketPtr pkt)
case REG_RDT:
regs.rdt = val;
DPRINTF(EthernetSM, "RXS: RDT Updated.\n");
if (getDrainState() == Drainable::Running) {
if (getDrainState() == DrainState::Running) {
DPRINTF(EthernetSM, "RXS: RDT Fetching Descriptors!\n");
rxDescCache.fetchDescriptors();
} else {
@@ -626,7 +626,7 @@ IGbE::write(PacketPtr pkt)
case REG_TDT:
regs.tdt = val;
DPRINTF(EthernetSM, "TXS: TX Tail pointer updated\n");
if (getDrainState() == Drainable::Running) {
if (getDrainState() == DrainState::Running) {
DPRINTF(EthernetSM, "TXS: TDT Fetching Descriptors!\n");
txDescCache.fetchDescriptors();
} else {
@@ -905,7 +905,7 @@ void
IGbE::DescCache<T>::writeback1()
{
// If we're draining delay issuing this DMA
if (igbe->getDrainState() != Drainable::Running) {
if (igbe->getDrainState() != DrainState::Running) {
igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay);
return;
}
@@ -986,7 +986,7 @@ void
IGbE::DescCache<T>::fetchDescriptors1()
{
// If we're draining delay issuing this DMA
if (igbe->getDrainState() != Drainable::Running) {
if (igbe->getDrainState() != DrainState::Running) {
igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay);
return;
}
@@ -2051,7 +2051,7 @@ void
IGbE::restartClock()
{
if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) &&
getDrainState() == Drainable::Running)
getDrainState() == DrainState::Running)
schedule(tickEvent, clockEdge(Cycles(1)));
}
@@ -2075,9 +2075,9 @@ IGbE::drain(DrainManager *dm)
if (count) {
DPRINTF(Drain, "IGbE not drained\n");
setDrainState(Drainable::Draining);
setDrainState(DrainState::Draining);
} else
setDrainState(Drainable::Drained);
setDrainState(DrainState::Drained);
return count;
}

4
src/dev/i8254xGBe.hh
View File

@@ -352,7 +352,7 @@ class IGbE : public EtherDevice
virtual void updateHead(long h) { igbe->regs.rdh(h); }
virtual void enableSm();
virtual void fetchAfterWb() {
if (!igbe->rxTick && igbe->getDrainState() == Drainable::Running)
if (!igbe->rxTick && igbe->getDrainState() == DrainState::Running)
fetchDescriptors();
}
@@ -414,7 +414,7 @@ class IGbE : public EtherDevice
virtual void enableSm();
virtual void actionAfterWb();
virtual void fetchAfterWb() {
if (!igbe->txTick && igbe->getDrainState() == Drainable::Running)
if (!igbe->txTick && igbe->getDrainState() == DrainState::Running)
fetchDescriptors();
}

6
src/dev/ide_disk.cc
View File

@@ -342,7 +342,7 @@ IdeDisk::doDmaTransfer()
panic("Inconsistent DMA transfer state: dmaState = %d devState = %d\n",
dmaState, devState);
if (ctrl->dmaPending() || ctrl->getDrainState() != Drainable::Running) {
if (ctrl->dmaPending() || ctrl->getDrainState() != DrainState::Running) {
schedule(dmaTransferEvent, curTick() + DMA_BACKOFF_PERIOD);
return;
} else
@@ -436,7 +436,7 @@ IdeDisk::doDmaRead()
curPrd.getByteCount(), TheISA::PageBytes);
}
if (ctrl->dmaPending() || ctrl->getDrainState() != Drainable::Running) {
if (ctrl->dmaPending() || ctrl->getDrainState() != DrainState::Running) {
schedule(dmaReadWaitEvent, curTick() + DMA_BACKOFF_PERIOD);
return;
} else if (!dmaReadCG->done()) {
@@ -518,7 +518,7 @@ IdeDisk::doDmaWrite()
dmaWriteCG = new ChunkGenerator(curPrd.getBaseAddr(),
curPrd.getByteCount(), TheISA::PageBytes);
}
if (ctrl->dmaPending() || ctrl->getDrainState() != Drainable::Running) {
if (ctrl->dmaPending() || ctrl->getDrainState() != DrainState::Running) {
schedule(dmaWriteWaitEvent, curTick() + DMA_BACKOFF_PERIOD);
DPRINTF(IdeDisk, "doDmaWrite: rescheduling\n");
return;

4
src/dev/io_device.cc
View File

@@ -99,9 +99,9 @@ PioDevice::drain(DrainManager *dm)
unsigned int count;
count = pioPort.drain(dm);
if (count)
setDrainState(Drainable::Draining);
setDrainState(DrainState::Draining);
else
setDrainState(Drainable::Drained);
setDrainState(DrainState::Drained);
return count;
}

8
src/dev/ns_gige.cc
View File

@@ -1068,7 +1068,7 @@ NSGigE::doRxDmaRead()
assert(rxDmaState == dmaIdle || rxDmaState == dmaReadWaiting);
rxDmaState = dmaReading;
if (dmaPending() || getDrainState() != Drainable::Running)
if (dmaPending() || getDrainState() != DrainState::Running)
rxDmaState = dmaReadWaiting;
else
dmaRead(rxDmaAddr, rxDmaLen, &rxDmaReadEvent, (uint8_t*)rxDmaData);
@@ -1099,7 +1099,7 @@ NSGigE::doRxDmaWrite()
assert(rxDmaState == dmaIdle || rxDmaState == dmaWriteWaiting);
rxDmaState = dmaWriting;
if (dmaPending() || getDrainState() != Running)
if (dmaPending() || getDrainState() != DrainState::Running)
rxDmaState = dmaWriteWaiting;
else
dmaWrite(rxDmaAddr, rxDmaLen, &rxDmaWriteEvent, (uint8_t*)rxDmaData);
@@ -1515,7 +1515,7 @@ NSGigE::doTxDmaRead()
assert(txDmaState == dmaIdle || txDmaState == dmaReadWaiting);
txDmaState = dmaReading;
if (dmaPending() || getDrainState() != Running)
if (dmaPending() || getDrainState() != DrainState::Running)
txDmaState = dmaReadWaiting;
else
dmaRead(txDmaAddr, txDmaLen, &txDmaReadEvent, (uint8_t*)txDmaData);
@@ -1546,7 +1546,7 @@ NSGigE::doTxDmaWrite()
assert(txDmaState == dmaIdle || txDmaState == dmaWriteWaiting);
txDmaState = dmaWriting;
if (dmaPending() || getDrainState() != Running)
if (dmaPending() || getDrainState() != DrainState::Running)
txDmaState = dmaWriteWaiting;
else
dmaWrite(txDmaAddr, txDmaLen, &txDmaWriteEvent, (uint8_t*)txDmaData);

4
src/dev/pcidev.cc
View File

@@ -261,9 +261,9 @@ PciDevice::drain(DrainManager *dm)
unsigned int count;
count = pioPort.drain(dm) + dmaPort.drain(dm) + configPort.drain(dm);
if (count)
setDrainState(Drainable::Draining);
setDrainState(DrainState::Draining);
else
setDrainState(Drainable::Drained);
setDrainState(DrainState::Drained);
return count;
}

4
src/dev/sinic.cc
View File

@@ -868,7 +868,7 @@ Device::rxKick()
break;
case rxBeginCopy:
if (dmaPending() || getDrainState() != Drainable::Running)
if (dmaPending() || getDrainState() != DrainState::Running)
goto exit;
rxDmaAddr = params()->platform->pciToDma(
@@ -1068,7 +1068,7 @@ Device::txKick()
break;
case txBeginCopy:
if (dmaPending() || getDrainState() != Drainable::Running)
if (dmaPending() || getDrainState() != DrainState::Running)
goto exit;
txDmaAddr = params()->platform->pciToDma(