diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 77df2c05de..492a669b89 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -370,7 +370,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         }
 
         if (do_access) {
-            dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
+            dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
             dcache_pkt->allocate();
             dcache_pkt->set(data);
 
diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 8de02f5337..8cd3567684 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -99,7 +99,7 @@ MemCmd::commandInfo[] =
             InvalidCmd, "ReadExResp" },
     /* LoadLockedReq */
     { SET4(IsRead, IsLocked, IsRequest, NeedsResponse),
-            ReadResp, "LoadLockedReq" },
+            LoadLockedResp, "LoadLockedReq" },
     /* LoadLockedResp */
     { SET4(IsRead, IsLocked, IsResponse, HasData),
             InvalidCmd, "LoadLockedResp" },