tick: rename Clock namespace to SimClock
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@@ -80,7 +80,7 @@ TsunamiIO::TsunamiIO(const Params *p)
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Tick
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TsunamiIO::frequency() const
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{
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return Clock::Frequency / params()->frequency;
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return SimClock::Frequency / params()->frequency;
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}
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Tick
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@@ -94,8 +94,8 @@ void
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EtherDump::dumpPacket(EthPacketPtr &packet)
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{
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pcap_pkthdr pkthdr;
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pkthdr.seconds = curTick / Clock::Int::s;
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pkthdr.microseconds = (curTick / Clock::Int::us) % ULL(1000000);
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pkthdr.seconds = curTick / SimClock::Int::s;
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pkthdr.microseconds = (curTick / SimClock::Int::us) % ULL(1000000);
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pkthdr.caplen = std::min(packet->length, maxlen);
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pkthdr.len = packet->length;
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stream->write(reinterpret_cast<char *>(&pkthdr), sizeof(pkthdr));
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@@ -693,7 +693,7 @@ IGbE::postInterrupt(IntTypes t, bool now)
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regs.icr = regs.icr() | t;
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Tick itr_interval = Clock::Int::ns * 256 * regs.itr.interval();
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Tick itr_interval = SimClock::Int::ns * 256 * regs.itr.interval();
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DPRINTF(EthernetIntr,
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"EINT: postInterrupt() curTick: %d itr: %d interval: %d\n",
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curTick, regs.itr.interval(), itr_interval);
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@@ -801,7 +801,7 @@ IGbE::chkInterrupt()
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DPRINTF(Ethernet,
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"Possibly scheduling interrupt because of imr write\n");
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if (!interEvent.scheduled()) {
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Tick t = curTick + Clock::Int::ns * 256 * regs.itr.interval();
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Tick t = curTick + SimClock::Int::ns * 256 * regs.itr.interval();
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DPRINTF(Ethernet, "Scheduling for %d\n", t);
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schedule(interEvent, t);
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}
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@@ -171,7 +171,7 @@ class IGbE : public EtherDevice
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*/
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void cpuClearInt();
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Tick intClock() { return Clock::Int::ns * 1024; }
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Tick intClock() { return SimClock::Int::ns * 1024; }
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/** This function is used to restart the clock so it can handle things like
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* draining and resume in one place. */
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@@ -255,7 +255,7 @@ Intel8254Timer::Counter::unserialize(const string &base, Checkpoint *cp,
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Intel8254Timer::Counter::CounterEvent::CounterEvent(Counter* c_ptr)
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{
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interval = (Tick)(Clock::Float::s / 1193180.0);
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interval = (Tick)(SimClock::Float::s / 1193180.0);
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counter = c_ptr;
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}
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@@ -271,7 +271,7 @@ void
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MC146818::RTCTickEvent::process()
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{
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DPRINTF(MC146818, "RTC clock tick\n");
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parent->schedule(this, curTick + Clock::Int::s);
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parent->schedule(this, curTick + SimClock::Int::s);
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parent->tickClock();
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}
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@@ -71,7 +71,7 @@ class MC146818 : public EventManager
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RTCTickEvent(MC146818 * _parent) : parent(_parent)
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{
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parent->schedule(this, curTick + Clock::Int::s);
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parent->schedule(this, curTick + SimClock::Int::s);
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}
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/** Event process to occur at interrupt*/
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@@ -80,7 +80,7 @@ MaltaIO::MaltaIO(const Params *p)
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Tick
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MaltaIO::frequency() const
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{
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return Clock::Frequency / params()->frequency;
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return SimClock::Frequency / params()->frequency;
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}
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Tick
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@@ -90,7 +90,7 @@ Uart8250::IntrEvent::process()
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void
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Uart8250::IntrEvent::scheduleIntr()
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{
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static const Tick interval = 225 * Clock::Int::ns;
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static const Tick interval = 225 * SimClock::Int::ns;
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DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
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curTick + interval);
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if (!scheduled())
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@@ -217,7 +217,7 @@ Uart8250::write(PacketPtr pkt)
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if (UART_IER_THRI & IER)
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{
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DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
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if (curTick - lastTxInt > 225 * Clock::Int::ns) {
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if (curTick - lastTxInt > 225 * SimClock::Int::ns) {
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DPRINTF(Uart, "-- Interrupting Immediately... %d,%d\n",
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curTick, lastTxInt);
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txIntrEvent.process();
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