diff --git a/src/cpu/base.cc b/src/cpu/base.cc index b10c731e17..8121307d50 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -194,9 +194,11 @@ BaseCPU::BaseCPU(const Params &p, bool is_checker) // create a stat group object for each thread on this core fetchStats.reserve(numThreads); executeStats.reserve(numThreads); + commitStats.reserve(numThreads); for (int i = 0; i < numThreads; i++) { fetchStats.emplace_back(new FetchCPUStats(this, i)); executeStats.emplace_back(new ExecuteCPUStats(this, i)); + commitStats.emplace_back(new CommitCPUStats(this, i)); } } @@ -922,4 +924,72 @@ ExecuteCPUStats::ExecuteCPUStats(statistics::Group *parent, int thread_id) .prereq(numVecRegWrites); } +BaseCPU:: +CommitCPUStats::CommitCPUStats(statistics::Group *parent, int thread_id) + : statistics::Group(parent, csprintf("commitStats%i", thread_id).c_str()), + ADD_STAT(numMemRefs, statistics::units::Count::get(), + "Number of memory references committed"), + ADD_STAT(numFpInsts, statistics::units::Count::get(), + "Number of float instructions"), + ADD_STAT(numIntInsts, statistics::units::Count::get(), + "Number of integer instructions"), + ADD_STAT(numLoadInsts, statistics::units::Count::get(), + "Number of load instructions"), + ADD_STAT(numStoreInsts, statistics::units::Count::get(), + "Number of store instructions"), + ADD_STAT(numVecInsts, statistics::units::Count::get(), + "Number of vector instructions"), + ADD_STAT(committedInstType, statistics::units::Count::get(), + "Class of committed instruction."), + ADD_STAT(committedControl, statistics::units::Count::get(), + "Class of control type instructions committed") +{ + committedInstType + .init(enums::Num_OpClass) + .flags(statistics::total | statistics::pdf | statistics::dist); + + for (unsigned i = 0; i < Num_OpClasses; ++i) { + committedInstType.subname(i, enums::OpClassStrings[i]); + } + + committedControl + .init(StaticInstFlags::Flags::Num_Flags) + .flags(statistics::nozero); + + for (unsigned i = 0; i < StaticInstFlags::Flags::Num_Flags; i++) { + committedControl.subname(i, StaticInstFlags::FlagsStrings[i]); + } +} + + +void +BaseCPU:: +CommitCPUStats::updateComCtrlStats(const StaticInstPtr staticInst) +{ + /* Add a count for every control instruction type */ + if (staticInst->isControl()) { + if (staticInst->isReturn()) { + committedControl[gem5::StaticInstFlags::Flags::IsReturn]++; + } + if (staticInst->isCall()) { + committedControl[gem5::StaticInstFlags::Flags::IsCall]++; + } + if (staticInst->isDirectCtrl()) { + committedControl[gem5::StaticInstFlags::Flags::IsDirectControl]++; + } + if (staticInst->isIndirectCtrl()) { + committedControl + [gem5::StaticInstFlags::Flags::IsIndirectControl]++; + } + if (staticInst->isCondCtrl()) { + committedControl[gem5::StaticInstFlags::Flags::IsCondControl]++; + } + if (staticInst->isUncondCtrl()) { + committedControl[gem5::StaticInstFlags::Flags::IsUncondControl]++; + } + committedControl[gem5::StaticInstFlags::Flags::IsControl]++; + } + +} + } // namespace gem5 diff --git a/src/cpu/base.hh b/src/cpu/base.hh index ad6fa469a3..5b2e97f8b0 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -738,8 +738,40 @@ class BaseCPU : public ClockedObject statistics::Scalar numDiscardedOps; }; + struct CommitCPUStats: public statistics::Group + { + CommitCPUStats(statistics::Group *parent, int thread_id); + + /* Number of committed memory references. */ + statistics::Scalar numMemRefs; + + /* Number of float instructions */ + statistics::Scalar numFpInsts; + + /* Number of int instructions */ + statistics::Scalar numIntInsts; + + /* number of load instructions */ + statistics::Scalar numLoadInsts; + + /* Number of store instructions */ + statistics::Scalar numStoreInsts; + + /* Number of vector instructions */ + statistics::Scalar numVecInsts; + + /* Number of instructions committed by type (OpClass) */ + statistics::Vector committedInstType; + + /* number of control instructions committed by control inst type */ + statistics::Vector committedControl; + void updateComCtrlStats(const StaticInstPtr staticInst); + + }; + std::vector> fetchStats; std::vector> executeStats; + std::vector> commitStats; }; } // namespace gem5 diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc index d657de5225..5c0354bb8a 100644 --- a/src/cpu/minor/execute.cc +++ b/src/cpu/minor/execute.cc @@ -879,41 +879,8 @@ Execute::doInstCommitAccounting(MinorDynInstPtr inst) thread->numOp++; thread->threadStats.numOps++; cpu.stats.numOps++; - cpu.stats.committedInstType[inst->id.threadId] - [inst->staticInst->opClass()]++; - - /** Add a count for every control instruction */ - if (inst->staticInst->isControl()) { - if (inst->staticInst->isReturn()) { - cpu.stats.committedControl[inst->id.threadId] - [gem5::StaticInstFlags::Flags::IsReturn]++; - } - if (inst->staticInst->isCall()) { - cpu.stats.committedControl[inst->id.threadId] - [gem5::StaticInstFlags::Flags::IsCall]++; - } - if (inst->staticInst->isDirectCtrl()) { - cpu.stats.committedControl[inst->id.threadId] - [gem5::StaticInstFlags::Flags::IsDirectControl]++; - } - if (inst->staticInst->isIndirectCtrl()) { - cpu.stats.committedControl[inst->id.threadId] - [gem5::StaticInstFlags::Flags::IsIndirectControl]++; - } - if (inst->staticInst->isCondCtrl()) { - cpu.stats.committedControl[inst->id.threadId] - [gem5::StaticInstFlags::Flags::IsCondControl]++; - } - if (inst->staticInst->isUncondCtrl()) { - cpu.stats.committedControl[inst->id.threadId] - [gem5::StaticInstFlags::Flags::IsUncondControl]++; - - } - cpu.stats.committedControl[inst->id.threadId] - [gem5::StaticInstFlags::Flags::IsControl]++; - } - - + cpu.commitStats[inst->id.threadId] + ->committedInstType[inst->staticInst->opClass()]++; /* Set the CP SeqNum to the numOps commit number */ if (inst->traceData) diff --git a/src/cpu/minor/stats.cc b/src/cpu/minor/stats.cc index 10e7573afd..b20ce95ec8 100644 --- a/src/cpu/minor/stats.cc +++ b/src/cpu/minor/stats.cc @@ -57,11 +57,7 @@ MinorStats::MinorStats(BaseCPU *base_cpu) "CPI: cycles per instruction"), ADD_STAT(ipc, statistics::units::Rate< statistics::units::Count, statistics::units::Cycle>::get(), - "IPC: instructions per cycle"), - ADD_STAT(committedInstType, statistics::units::Count::get(), - "Class of committed instruction"), - ADD_STAT(committedControl, statistics::units::Count::get(), - "Class of control type instructions committed") + "IPC: instructions per cycle") { quiesceCycles.prereq(quiesceCycles); @@ -72,15 +68,6 @@ MinorStats::MinorStats(BaseCPU *base_cpu) ipc.precision(6); ipc = numInsts / base_cpu->baseStats.numCycles; - committedInstType - .init(base_cpu->numThreads, enums::Num_OpClass) - .flags(statistics::total | statistics::pdf | statistics::dist); - committedInstType.ysubnames(enums::OpClassStrings); - - committedControl - .init(base_cpu->numThreads, StaticInstFlags::Flags::Num_Flags) - .flags(statistics::nozero); - committedControl.ysubnames(StaticInstFlags::FlagsStrings); } } // namespace minor diff --git a/src/cpu/minor/stats.hh b/src/cpu/minor/stats.hh index e5d018679d..f7d5e71dfa 100644 --- a/src/cpu/minor/stats.hh +++ b/src/cpu/minor/stats.hh @@ -72,12 +72,6 @@ struct MinorStats : public statistics::Group statistics::Formula cpi; statistics::Formula ipc; - /** Number of instructions by type (OpClass) */ - statistics::Vector2d committedInstType; - - /** Number of branches commited */ - statistics::Vector2d committedControl; - }; } // namespace minor diff --git a/src/cpu/o3/commit.cc b/src/cpu/o3/commit.cc index 38dce831b1..7419b2a2f9 100644 --- a/src/cpu/o3/commit.cc +++ b/src/cpu/o3/commit.cc @@ -160,21 +160,10 @@ Commit::CommitStats::CommitStats(CPU *cpu, Commit *commit) "Number of instructions committed"), ADD_STAT(opsCommitted, statistics::units::Count::get(), "Number of ops (including micro ops) committed"), - ADD_STAT(memRefs, statistics::units::Count::get(), - "Number of memory references committed"), - ADD_STAT(loads, statistics::units::Count::get(), "Number of loads committed"), ADD_STAT(amos, statistics::units::Count::get(), "Number of atomic instructions committed"), ADD_STAT(membars, statistics::units::Count::get(), "Number of memory barriers committed"), - ADD_STAT(branches, statistics::units::Count::get(), - "Number of branches committed"), - ADD_STAT(vectorInstructions, statistics::units::Count::get(), - "Number of committed Vector instructions."), - ADD_STAT(floating, statistics::units::Count::get(), - "Number of committed floating point instructions."), - ADD_STAT(integer, statistics::units::Count::get(), - "Number of committed integer instructions."), ADD_STAT(functionCalls, statistics::units::Count::get(), "Number of function calls committed."), ADD_STAT(committedInstType, statistics::units::Count::get(), @@ -200,14 +189,6 @@ Commit::CommitStats::CommitStats(CPU *cpu, Commit *commit) .init(cpu->numThreads) .flags(total); - memRefs - .init(cpu->numThreads) - .flags(total); - - loads - .init(cpu->numThreads) - .flags(total); - amos .init(cpu->numThreads) .flags(total); @@ -216,22 +197,6 @@ Commit::CommitStats::CommitStats(CPU *cpu, Commit *commit) .init(cpu->numThreads) .flags(total); - branches - .init(cpu->numThreads) - .flags(total); - - vectorInstructions - .init(cpu->numThreads) - .flags(total); - - floating - .init(cpu->numThreads) - .flags(total); - - integer - .init(cpu->numThreads) - .flags(total); - functionCalls .init(commit->numThreads) .flags(total); @@ -1396,21 +1361,20 @@ Commit::updateComInstStats(const DynInstPtr &inst) // // Control Instructions // - if (inst->isControl()) - stats.branches[tid]++; + cpu->commitStats[tid]->updateComCtrlStats(inst->staticInst); // // Memory references // if (inst->isMemRef()) { - stats.memRefs[tid]++; + cpu->commitStats[tid]->numMemRefs++; if (inst->isLoad()) { - stats.loads[tid]++; + cpu->commitStats[tid]->numLoadInsts++; } - if (inst->isAtomic()) { - stats.amos[tid]++; + if (inst->isStore()) { + cpu->commitStats[tid]->numStoreInsts++; } } @@ -1420,14 +1384,14 @@ Commit::updateComInstStats(const DynInstPtr &inst) // Integer Instruction if (inst->isInteger()) - stats.integer[tid]++; + cpu->commitStats[tid]->numIntInsts++; // Floating Point Instruction if (inst->isFloating()) - stats.floating[tid]++; + cpu->commitStats[tid]->numFpInsts++; // Vector Instruction if (inst->isVector()) - stats.vectorInstructions[tid]++; + cpu->commitStats[tid]->numVecInsts++; // Function Calls if (inst->isCall()) diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index cf4eaf5d92..6591360197 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -483,22 +483,10 @@ class Commit statistics::Vector instsCommitted; /** Total number of ops (including micro ops) committed. */ statistics::Vector opsCommitted; - /** Stat for the total number of committed memory references. */ - statistics::Vector memRefs; - /** Stat for the total number of committed loads. */ - statistics::Vector loads; /** Stat for the total number of committed atomics. */ statistics::Vector amos; /** Total number of committed memory barriers. */ statistics::Vector membars; - /** Total number of committed branches. */ - statistics::Vector branches; - /** Total number of vector instructions */ - statistics::Vector vectorInstructions; - /** Total number of floating point instructions */ - statistics::Vector floating; - /** Total number of integer instructions */ - statistics::Vector integer; /** Total number of function calls */ statistics::Vector functionCalls; /** Committed instructions by instruction type (OpClass) */ diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index c8d9aeeb86..70da65953b 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -403,19 +403,19 @@ BaseSimpleCPU::postExecute() //integer alu accesses if (curStaticInst->isInteger()){ executeStats[t_info.thread->threadId()]->numIntAluAccesses++; - t_info.execContextStats.numIntInsts++; + commitStats[t_info.thread->threadId()]->numIntInsts++; } //float alu accesses if (curStaticInst->isFloating()){ executeStats[t_info.thread->threadId()]->numFpAluAccesses++; - t_info.execContextStats.numFpInsts++; + commitStats[t_info.thread->threadId()]->numFpInsts++; } //vector alu accesses if (curStaticInst->isVector()){ executeStats[t_info.thread->threadId()]->numVecAluAccesses++; - t_info.execContextStats.numVecInsts++; + commitStats[t_info.thread->threadId()]->numVecInsts++; } //Matrix alu accesses @@ -429,22 +429,19 @@ BaseSimpleCPU::postExecute() t_info.execContextStats.numCallsReturns++; } - //the number of branch predictions that will be made - if (curStaticInst->isCondCtrl()){ - t_info.execContextStats.numCondCtrlInsts++; - } - //result bus acceses if (curStaticInst->isLoad()){ - t_info.execContextStats.numLoadInsts++; + commitStats[t_info.thread->threadId()]->numLoadInsts++; } if (curStaticInst->isStore() || curStaticInst->isAtomic()){ - t_info.execContextStats.numStoreInsts++; + commitStats[t_info.thread->threadId()]->numStoreInsts++; } /* End power model statistics */ - t_info.execContextStats.statExecutedInstType[curStaticInst->opClass()]++; + commitStats[t_info.thread->threadId()] + ->committedInstType[curStaticInst->opClass()]++; + commitStats[t_info.thread->threadId()]->updateComCtrlStats(curStaticInst); if (FullSystem) traceFunctions(instAddr); diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index 00efd8593c..42d6181cf2 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -94,20 +94,8 @@ class SimpleExecContext : public ExecContext "Number of matrix alu accesses"), ADD_STAT(numCallsReturns, statistics::units::Count::get(), "Number of times a function call or return occured"), - ADD_STAT(numCondCtrlInsts, statistics::units::Count::get(), - "Number of instructions that are conditional controls"), - ADD_STAT(numIntInsts, statistics::units::Count::get(), - "Number of integer instructions"), - ADD_STAT(numFpInsts, statistics::units::Count::get(), - "Number of float instructions"), - ADD_STAT(numVecInsts, statistics::units::Count::get(), - "Number of vector instructions"), ADD_STAT(numMatInsts, statistics::units::Count::get(), "Number of matrix instructions"), - ADD_STAT(numLoadInsts, statistics::units::Count::get(), - "Number of load instructions"), - ADD_STAT(numStoreInsts, statistics::units::Count::get(), - "Number of store instructions"), ADD_STAT(numIdleCycles, statistics::units::Cycle::get(), "Number of idle cycles"), ADD_STAT(numBusyCycles, statistics::units::Cycle::get(), @@ -120,8 +108,6 @@ class SimpleExecContext : public ExecContext "Number of branches predicted as taken"), ADD_STAT(numBranchMispred, statistics::units::Count::get(), "Number of branch mispredictions"), - ADD_STAT(statExecutedInstType, statistics::units::Count::get(), - "Class of executed instruction."), numRegReads{ &(cpu->executeStats[thread->threadId()]->numIntRegReads), &(cpu->executeStats[thread->threadId()]->numFpRegReads), @@ -142,13 +128,6 @@ class SimpleExecContext : public ExecContext &numMatRegWrites } { - statExecutedInstType - .init(enums::Num_OpClass) - .flags(statistics::total | statistics::pdf | statistics::dist); - - for (unsigned i = 0; i < Num_OpClasses; ++i) { - statExecutedInstType.subname(i, enums::OpClassStrings[i]); - } idleFraction = statistics::constant(1.0) - notIdleFraction; numIdleCycles = idleFraction * cpu->baseStats.numCycles; @@ -171,18 +150,6 @@ class SimpleExecContext : public ExecContext // Number of function calls/returns statistics::Scalar numCallsReturns; - // Conditional control instructions; - statistics::Scalar numCondCtrlInsts; - - // Number of int instructions - statistics::Scalar numIntInsts; - - // Number of float instructions - statistics::Scalar numFpInsts; - - // Number of vector instructions - statistics::Scalar numVecInsts; - // Number of matrix instructions statistics::Scalar numMatInsts; @@ -190,10 +157,6 @@ class SimpleExecContext : public ExecContext mutable statistics::Scalar numMatRegReads; statistics::Scalar numMatRegWrites; - // Number of simulated memory references - statistics::Scalar numLoadInsts; - statistics::Scalar numStoreInsts; - // Number of idle cycles statistics::Formula numIdleCycles; @@ -211,9 +174,6 @@ class SimpleExecContext : public ExecContext statistics::Scalar numBranchMispred; /// @} - // Instruction mix histogram by OpClass - statistics::Vector statExecutedInstType; - std::array numRegReads; std::array numRegWrites;