diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index 2e61d027f2..b3200ec0b9 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -55,5 +55,6 @@ class X86TLB(BaseTLB):
     cxx_class = 'X86ISA::TLB'
     cxx_header = 'arch/x86/tlb.hh'
     size = Param.Unsigned(64, "TLB size")
+    system = Param.System(Parent.any, "system object")
     walker = Param.X86PagetableWalker(\
             X86PagetableWalker(), "page table walker")
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 2985a8bcb1..65ed9c01d4 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -61,7 +61,7 @@ namespace X86ISA {
 
 TLB::TLB(const Params *p)
     : BaseTLB(p), configAddress(0), size(p->size),
-      tlb(size), lruSeq(0)
+      tlb(size), lruSeq(0), m5opRange(p->system->m5opRange())
 {
     if (!size)
         fatal("TLBs must have a non-zero size.\n");
@@ -229,8 +229,6 @@ TLB::finalizePhysical(const RequestPtr &req,
 {
     Addr paddr = req->getPaddr();
 
-    AddrRange m5opRange(0xFFFF0000, 0x100000000);
-
     if (m5opRange.contains(paddr)) {
         req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
                       Request::STRICT_ORDER);
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index b969bca9de..21bd6401c7 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -100,6 +100,8 @@ namespace X86ISA
         TlbEntryTrie trie;
         uint64_t lruSeq;
 
+        AddrRange m5opRange;
+
         // Statistics
         Stats::Scalar rdAccesses;
         Stats::Scalar wrAccesses;