scons: Put all config variables in an env['CONF'] sub-dict.

This makes what are configuration and what are internal SCons variables
explicit and separate, and makes it unnecessary to call out what
variables to export to C++.

These variables will also be plumbed into and out of kconfiglib in later
changes.

Change-Id: Iaf5e098d7404af06285c421dbdf8ef4171b3f001
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56892
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/SConscript

@@ -61,7 +61,7 @@ Source('insts/vfp.cc', tags='arm isa')
 Source('insts/fplib.cc', tags='arm isa')
 Source('insts/crypto.cc', tags='arm isa')
 Source('insts/tme64.cc', tags='arm isa')
-if env['PROTOCOL'] == 'MESI_Three_Level_HTM':
+if env['CONF']['PROTOCOL'] == 'MESI_Three_Level_HTM':
     Source('insts/tme64ruby.cc', tags='arm isa')
 else:
     Source('insts/tme64classic.cc', tags='arm isa')
@@ -113,13 +113,12 @@ SimObject('ArmTLB.py', sim_objects=['ArmTLB'], enums=['ArmLookupLevel'],
 SimObject('ArmPMU.py', sim_objects=['ArmPMU'], tags='arm isa')
 
 SimObject('ArmCPU.py', sim_objects=[], tags='arm isa')
-if env['TARGET_ISA'] == 'arm':
-    SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='arm isa')
-    SimObject('TimingSimpleCPU.py', sim_objects=[], tags='arm isa')
-    SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='arm isa')
-    SimObject('O3CPU.py', sim_objects=[], tags='arm isa')
-    SimObject('O3Checker.py', sim_objects=[], tags='arm isa')
-    SimObject('MinorCPU.py', sim_objects=[], tags='arm isa')
+SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='arm isa')
+SimObject('TimingSimpleCPU.py', sim_objects=[], tags='arm isa')
+SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='arm isa')
+SimObject('O3CPU.py', sim_objects=[], tags='arm isa')
+SimObject('O3Checker.py', sim_objects=[], tags='arm isa')
+SimObject('MinorCPU.py', sim_objects=[], tags='arm isa')
 
 DebugFlag('Arm', tags='arm isa')
 DebugFlag('ArmTme', 'Transactional Memory Extension', tags='arm isa')

src/arch/arm/fastmodel/CortexA76/SConscript

@@ -25,7 +25,7 @@
 
 Import('*')
 
-if not env['USE_ARM_FASTMODEL']:
+if not env['CONF']['USE_ARM_FASTMODEL']:
     Return()
 
 protocol_dir = Dir('..').Dir('protocol')

src/arch/arm/fastmodel/CortexR52/SConscript

@@ -25,7 +25,7 @@
 
 Import('*')
 
-if not env['USE_ARM_FASTMODEL']:
+if not env['CONF']['USE_ARM_FASTMODEL']:
     Return()
 
 protocol_dir = Dir('..').Dir('protocol')

src/arch/arm/fastmodel/GIC/SConscript

@@ -25,7 +25,7 @@
 
 Import('*')
 
-if not env['USE_ARM_FASTMODEL']:
+if not env['CONF']['USE_ARM_FASTMODEL']:
     Return()
 
 protocol_dir = Dir('..').Dir('protocol')

src/arch/arm/fastmodel/PL330_DMAC/SConscript

@@ -25,7 +25,7 @@
 
 Import('*')
 
-if not env['USE_ARM_FASTMODEL']:
+if not env['CONF']['USE_ARM_FASTMODEL']:
     Return()
 
 protocol_dir = Dir('..').Dir('protocol')

src/arch/arm/fastmodel/SConscript

@@ -46,13 +46,13 @@ from gem5_scons import Transform, warning, error
 
 import os.path
 
-if env['USE_ARM_FASTMODEL']:
-    if not env['USE_SYSTEMC']:
+if env['CONF']['USE_ARM_FASTMODEL']:
+    if not env['CONF']['USE_SYSTEMC']:
         warning('ARM Fast Models require systemc support')
-        env['USE_ARM_FASTMODEL'] = False
+        env['CONF']['USE_ARM_FASTMODEL'] = False
         Return()
 
-if not env['USE_ARM_FASTMODEL']:
+if not env['CONF']['USE_ARM_FASTMODEL']:
     Return()
 
 
@@ -60,7 +60,7 @@ systemc_home = Dir('#/src/systemc/ext/systemc_home')
 env['ENV']['SYSTEMC_HOME'] = systemc_home.abspath
 
 def extract_var(name):
-    if name not in env:
+    if name not in env['CONF']:
         error('Error: %s is not set' % name)
     print('%s = %s' % (name, env[name]))
     # Make sure the value of this variable shows up as an environment variable
@@ -77,7 +77,7 @@ maxcore_home = Dir(maxcore_home)
 armlmd_license_file = File(armlmd_license_file)
 
 
-pvlib_flavor = env['PVLIB_FLAVOR']
+pvlib_flavor = env['CONF']['PVLIB_FLAVOR']
 pvlib_lib_dir = pvlib_home.Dir('lib').Dir(pvlib_flavor)
 
 simulation_engine_name = 'libMAXCOREInitSimulationEngine.3.so'
@@ -254,7 +254,7 @@ class ProjectFileParser(Grammar):
         t[0] = t[1]
 
 
-license_count = int(env['ARMLMD_LICENSE_COUNT'])
+license_count = int(env['CONF']['ARMLMD_LICENSE_COUNT'])
 arm_licenses = list((Value(object()) for i in range(license_count)))
 license_cycle = cycle(arm_licenses)
 
@@ -348,8 +348,9 @@ class ArmFastModelComponent(object):
         # Simgen also puts required share library under the project folder.
         self.rpaths = [simgen_dir, project_file_dir]
         self.log = gen_dir.File('build_%s.log' % tlc)
-        self.simgen_cmd = env.subst('${SIMGEN} -p %s --configuration %s -b ' +
-            '--verbose off --num-build-cpus 100 --build-dir %s >%s') % \
+        self.simgen_cmd = env.subst('${CONF["SIMGEN"]} -p %s '
+            '--configuration %s -b --verbose off --num-build-cpus 100 '
+            '--build-dir %s >%s') % \
             (shlex.quote(project_file.srcnode().abspath),
              shlex.quote(config_name),
              shlex.quote(simgen_dir.abspath),

src/arch/arm/fastmodel/iris/SConscript

@@ -25,7 +25,7 @@
 
 Import('*')
 
-if not env['USE_ARM_FASTMODEL']:
+if not env['CONF']['USE_ARM_FASTMODEL']:
     Return()
 
 SimObject('Iris.py', sim_objects=[

src/arch/arm/fastmodel/reset_controller/SConscript

@@ -25,7 +25,7 @@
 
 Import('*')
 
-if not env['USE_ARM_FASTMODEL']:
+if not env['CONF']['USE_ARM_FASTMODEL']:
     Return()
 
 SimObject('FastModelResetControllerExample.py', sim_objects=[

src/arch/arm/kvm/SConscript

@@ -40,7 +40,7 @@ Import('*')
 import platform
 host_isa = platform.machine()
 
-if not (env['USE_KVM'] and env['KVM_ISA'] == 'arm'):
+if not (env['CONF']['USE_KVM'] and env['CONF']['KVM_ISA'] == 'arm'):
     Return()
 
 SimObject('KvmGic.py',