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scons: Put all config variables in an env['CONF'] sub-dict.

Browse Source 
This makes what are configuration and what are internal SCons variables
explicit and separate, and makes it unnecessary to call out what
variables to export to C++.

These variables will also be plumbed into and out of kconfiglib in later
changes.

Change-Id: Iaf5e098d7404af06285c421dbdf8ef4171b3f001
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56892
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2022-02-15 22:23:43 -08:00
parent caa5f12e21
commit e6c0ba97db
87 changed files with 211 additions and 233 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/arch/SConscript
View File

@@ -56,18 +56,18 @@ Import('*')
#
#################################################################
env.TagImplies(env.subst('${TARGET_ISA} isa'), 'gem5 lib')
env.TagImplies(env.subst('${CONF["TARGET_ISA"]} isa'), 'gem5 lib')
env.SwitchingHeaders(
Split('''
isa.hh
vecregs.hh
'''),
env.subst('${TARGET_ISA}'))
env.subst('${CONF["TARGET_ISA"]}'))
amdgpu_isa = ['gcn3', 'vega']
if env['BUILD_GPU']:
if env['CONF']['BUILD_GPU']:
env.SwitchingHeaders(
Split('''
gpu_decoder.hh
@@ -75,8 +75,9 @@ if env['BUILD_GPU']:
gpu_registers.hh
gpu_types.hh
'''),
'{}'.format('amdgpu/' if env['TARGET_GPU_ISA'] in amdgpu_isa else '')+
env.subst('${TARGET_GPU_ISA}'))
'{}'.format('amdgpu/' if
env['CONF']['TARGET_GPU_ISA'] in amdgpu_isa else '') +
env.subst('${CONF["TARGET_GPU_ISA"]}'))
#################################################################
#

4
src/arch/amdgpu/common/SConscript
View File

@@ -31,10 +31,10 @@ import sys
Import('*')
if not env['BUILD_GPU']:
if not env['CONF']['BUILD_GPU']:
Return()
if env['TARGET_GPU_ISA'] == 'gcn3' or env['TARGET_GPU_ISA'] == 'vega':
if env['CONF']['TARGET_GPU_ISA'] in ('gcn3', 'vega'):
SimObject('X86GPUTLB.py', sim_objects=['X86GPUTLB', 'TLBCoalescer'])
Source('tlb.cc')

4
src/arch/amdgpu/gcn3/SConscript
View File

@@ -33,10 +33,10 @@ import sys
Import('*')
if not env['BUILD_GPU']:
if not env['CONF']['BUILD_GPU']:
Return()
if env['TARGET_GPU_ISA'] == 'gcn3':
if env['CONF']['TARGET_GPU_ISA'] == 'gcn3':
Source('decoder.cc')
Source('insts/gpu_static_inst.cc')
Source('insts/instructions.cc')

4
src/arch/amdgpu/vega/SConscript
View File

@@ -33,7 +33,7 @@ import sys
Import('*')
if not env['BUILD_GPU']:
if not env['CONF']['BUILD_GPU']:
Return()
SimObject('VegaGPUTLB.py', sim_objects=['VegaPagetableWalker',
@@ -48,7 +48,7 @@ Source('tlb_coalescer.cc')
DebugFlag('GPUPTWalker', 'Debug flag for GPU page table walker')
if env['TARGET_GPU_ISA'] == 'vega':
if env['CONF']['TARGET_GPU_ISA'] == 'vega':
Source('decoder.cc')
Source('insts/gpu_static_inst.cc')
Source('insts/instructions.cc')

15
src/arch/arm/SConscript
View File

@@ -61,7 +61,7 @@ Source('insts/vfp.cc', tags='arm isa')
Source('insts/fplib.cc', tags='arm isa')
Source('insts/crypto.cc', tags='arm isa')
Source('insts/tme64.cc', tags='arm isa')
if env['PROTOCOL'] == 'MESI_Three_Level_HTM':
if env['CONF']['PROTOCOL'] == 'MESI_Three_Level_HTM':
Source('insts/tme64ruby.cc', tags='arm isa')
else:
Source('insts/tme64classic.cc', tags='arm isa')
@@ -113,13 +113,12 @@ SimObject('ArmTLB.py', sim_objects=['ArmTLB'], enums=['ArmLookupLevel'],
SimObject('ArmPMU.py', sim_objects=['ArmPMU'], tags='arm isa')
SimObject('ArmCPU.py', sim_objects=[], tags='arm isa')
if env['TARGET_ISA'] == 'arm':
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='arm isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='arm isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='arm isa')
SimObject('O3CPU.py', sim_objects=[], tags='arm isa')
SimObject('O3Checker.py', sim_objects=[], tags='arm isa')
SimObject('MinorCPU.py', sim_objects=[], tags='arm isa')
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='arm isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='arm isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='arm isa')
SimObject('O3CPU.py', sim_objects=[], tags='arm isa')
SimObject('O3Checker.py', sim_objects=[], tags='arm isa')
SimObject('MinorCPU.py', sim_objects=[], tags='arm isa')
DebugFlag('Arm', tags='arm isa')
DebugFlag('ArmTme', 'Transactional Memory Extension', tags='arm isa')

2
src/arch/arm/fastmodel/CortexA76/SConscript
View File

@@ -25,7 +25,7 @@
Import('*')
if not env['USE_ARM_FASTMODEL']:
if not env['CONF']['USE_ARM_FASTMODEL']:
Return()
protocol_dir = Dir('..').Dir('protocol')

2
src/arch/arm/fastmodel/CortexR52/SConscript
View File

@@ -25,7 +25,7 @@
Import('*')
if not env['USE_ARM_FASTMODEL']:
if not env['CONF']['USE_ARM_FASTMODEL']:
Return()
protocol_dir = Dir('..').Dir('protocol')

2
src/arch/arm/fastmodel/GIC/SConscript
View File

@@ -25,7 +25,7 @@
Import('*')
if not env['USE_ARM_FASTMODEL']:
if not env['CONF']['USE_ARM_FASTMODEL']:
Return()
protocol_dir = Dir('..').Dir('protocol')

2
src/arch/arm/fastmodel/PL330_DMAC/SConscript
View File

@@ -25,7 +25,7 @@
Import('*')
if not env['USE_ARM_FASTMODEL']:
if not env['CONF']['USE_ARM_FASTMODEL']:
Return()
protocol_dir = Dir('..').Dir('protocol')

19
src/arch/arm/fastmodel/SConscript
View File

@@ -46,13 +46,13 @@ from gem5_scons import Transform, warning, error
import os.path
if env['USE_ARM_FASTMODEL']:
if not env['USE_SYSTEMC']:
if env['CONF']['USE_ARM_FASTMODEL']:
if not env['CONF']['USE_SYSTEMC']:
warning('ARM Fast Models require systemc support')
env['USE_ARM_FASTMODEL'] = False
env['CONF']['USE_ARM_FASTMODEL'] = False
Return()
if not env['USE_ARM_FASTMODEL']:
if not env['CONF']['USE_ARM_FASTMODEL']:
Return()
@@ -60,7 +60,7 @@ systemc_home = Dir('#/src/systemc/ext/systemc_home')
env['ENV']['SYSTEMC_HOME'] = systemc_home.abspath
def extract_var(name):
if name not in env:
if name not in env['CONF']:
error('Error: %s is not set' % name)
print('%s = %s' % (name, env[name]))
# Make sure the value of this variable shows up as an environment variable
@@ -77,7 +77,7 @@ maxcore_home = Dir(maxcore_home)
armlmd_license_file = File(armlmd_license_file)
pvlib_flavor = env['PVLIB_FLAVOR']
pvlib_flavor = env['CONF']['PVLIB_FLAVOR']
pvlib_lib_dir = pvlib_home.Dir('lib').Dir(pvlib_flavor)
simulation_engine_name = 'libMAXCOREInitSimulationEngine.3.so'
@@ -254,7 +254,7 @@ class ProjectFileParser(Grammar):
t[0] = t[1]
license_count = int(env['ARMLMD_LICENSE_COUNT'])
license_count = int(env['CONF']['ARMLMD_LICENSE_COUNT'])
arm_licenses = list((Value(object()) for i in range(license_count)))
license_cycle = cycle(arm_licenses)
@@ -348,8 +348,9 @@ class ArmFastModelComponent(object):
# Simgen also puts required share library under the project folder.
self.rpaths = [simgen_dir, project_file_dir]
self.log = gen_dir.File('build_%s.log' % tlc)
self.simgen_cmd = env.subst('${SIMGEN} -p %s --configuration %s -b ' +
'--verbose off --num-build-cpus 100 --build-dir %s >%s') % \
self.simgen_cmd = env.subst('${CONF["SIMGEN"]} -p %s '
'--configuration %s -b --verbose off --num-build-cpus 100 '
'--build-dir %s >%s') % \
(shlex.quote(project_file.srcnode().abspath),
shlex.quote(config_name),
shlex.quote(simgen_dir.abspath),

2
src/arch/arm/fastmodel/iris/SConscript
View File

@@ -25,7 +25,7 @@
Import('*')
if not env['USE_ARM_FASTMODEL']:
if not env['CONF']['USE_ARM_FASTMODEL']:
Return()
SimObject('Iris.py', sim_objects=[

2
src/arch/arm/fastmodel/reset_controller/SConscript
View File

@@ -25,7 +25,7 @@
Import('*')
if not env['USE_ARM_FASTMODEL']:
if not env['CONF']['USE_ARM_FASTMODEL']:
Return()
SimObject('FastModelResetControllerExample.py', sim_objects=[

2
src/arch/arm/kvm/SConscript
View File

@@ -40,7 +40,7 @@ Import('*')
import platform
host_isa = platform.machine()
if not (env['USE_KVM'] and env['KVM_ISA'] == 'arm'):
if not (env['CONF']['USE_KVM'] and env['CONF']['KVM_ISA'] == 'arm'):
Return()
SimObject('KvmGic.py',

9
src/arch/mips/SConscript
View File

@@ -52,11 +52,10 @@ SimObject('MipsSeWorkload.py', sim_objects=['MipsSEWorkload', 'MipsEmuLinux'],
SimObject('MipsTLB.py', sim_objects=['MipsTLB'], tags='mips isa')
SimObject('MipsCPU.py', sim_objects=[], tags='mips isa')
if env['TARGET_ISA'] == 'mips':
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='mips isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='mips isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='mips isa')
SimObject('O3CPU.py', sim_objects=[], tags='mips isa')
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='mips isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='mips isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='mips isa')
SimObject('O3CPU.py', sim_objects=[], tags='mips isa')
DebugFlag('MipsPRA', tags='mips isa')

9
src/arch/power/SConscript
View File

@@ -56,11 +56,10 @@ SimObject('PowerSeWorkload.py', sim_objects=[
SimObject('PowerTLB.py', sim_objects=['PowerTLB'], tags='power isa')
SimObject('PowerCPU.py', sim_objects=[], tags='power isa')
if env['TARGET_ISA'] == 'power':
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='power isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='power isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='power isa')
SimObject('O3CPU.py', sim_objects=[], tags='power isa')
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='power isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='power isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='power isa')
SimObject('O3CPU.py', sim_objects=[], tags='power isa')
DebugFlag('Power', tags='power isa')

11
src/arch/riscv/SConscript
View File

@@ -75,12 +75,11 @@ SimObject('RiscvTLB.py', sim_objects=['RiscvPagetableWalker', 'RiscvTLB'],
tags='riscv isa')
SimObject('RiscvCPU.py', sim_objects=[], tags='riscv isa')
if env['TARGET_ISA'] == 'riscv':
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='riscv isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='riscv isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='riscv isa')
SimObject('O3CPU.py', sim_objects=[], tags='riscv isa')
SimObject('MinorCPU.py', sim_objects=[], tags='riscv isa')
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='riscv isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='riscv isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='riscv isa')
SimObject('O3CPU.py', sim_objects=[], tags='riscv isa')
SimObject('MinorCPU.py', sim_objects=[], tags='riscv isa')
DebugFlag('RiscvMisc', tags='riscv isa')
DebugFlag('PMP', tags='riscv isa')

9
src/arch/sparc/SConscript
View File

@@ -57,11 +57,10 @@ SimObject('SparcSeWorkload.py', sim_objects=[
SimObject('SparcTLB.py', sim_objects=['SparcTLB'], tags='sparc isa')
SimObject('SparcCPU.py', sim_objects=[], tags='sparc isa')
if env['TARGET_ISA'] == 'sparc':
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='sparc isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='sparc isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='sparc isa')
SimObject('O3CPU.py', sim_objects=[], tags='sparc isa')
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='sparc isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='sparc isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='sparc isa')
SimObject('O3CPU.py', sim_objects=[], tags='sparc isa')
DebugFlag('Sparc', "Generic SPARC ISA stuff", tags='sparc isa')
DebugFlag('RegisterWindows', "Register window manipulation", tags='sparc isa')

9
src/arch/x86/SConscript
View File

@@ -74,11 +74,10 @@ SimObject('X86TLB.py', sim_objects=['X86PagetableWalker', 'X86TLB'],
tags='x86 isa')
SimObject('X86CPU.py', sim_objects=[], tags='x86 isa')
if env['TARGET_ISA'] == 'x86':
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='x86 isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='x86 isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='x86 isa')
SimObject('O3CPU.py', sim_objects=[], tags='x86 isa')
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='x86 isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='x86 isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='x86 isa')
SimObject('O3CPU.py', sim_objects=[], tags='x86 isa')
DebugFlag('LocalApic', "Local APIC debugging", tags='x86 isa')
DebugFlag('X86', "Generic X86 ISA debugging", tags='x86 isa')

5
src/arch/x86/bare_metal/SConscript
View File

@@ -25,7 +25,4 @@
Import('*')
if env['TARGET_ISA'] != 'x86':
Return()
Source('workload.cc')
Source('workload.cc', tags='x86 isa')

3
src/arch/x86/kvm/SConscript
View File

@@ -37,7 +37,8 @@
Import('*')
if not env['USE_KVM'] or env['TARGET_ISA'] != env['KVM_ISA']:
if not env['CONF']['USE_KVM'] or \
env['CONF']['TARGET_ISA'] != env['CONF']['KVM_ISA']:
Return()
SimObject('X86KvmCPU.py', sim_objects=['X86KvmCPU'], tags='x86 isa')