configs: Connect SDMA, IH, and memory manager in GPUFS

Add the devices that have been added in previous changesets to the
config file. Forward MMIO writes to the appropriate device based
on the MMIO address. Connect doorbells and forward rings to the
appropriate device based on queue type.

Change-Id: I44110c9a24559936102a246c9658abb84a8ce07e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53065
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Alexandru Dutu
2021-09-03 13:51:44 -05:00
committed by Matthew Poremba
parent f1772d3505
commit e67e02d657
2 changed files with 56 additions and 0 deletions

View File

@@ -227,6 +227,29 @@ void
AMDGPUDevice::writeDoorbell(PacketPtr pkt, Addr offset)
{
DPRINTF(AMDGPUDevice, "Wrote doorbell %#lx\n", offset);
if (doorbells.find(offset) != doorbells.end()) {
QueueType q_type = doorbells[offset];
DPRINTF(AMDGPUDevice, "Doorbell offset %p queue: %d\n",
offset, q_type);
switch (q_type) {
case SDMAGfx: {
SDMAEngine *sdmaEng = getSDMAEngine(offset);
sdmaEng->processGfx(pkt->getLE<uint64_t>());
} break;
case SDMAPage: {
SDMAEngine *sdmaEng = getSDMAEngine(offset);
sdmaEng->processPage(pkt->getLE<uint64_t>());
} break;
case InterruptHandler:
deviceIH->updateRptr(pkt->getLE<uint32_t>());
break;
default:
panic("Write to unkown queue type!");
}
} else {
warn("Unknown doorbell offset: %lx\n", offset);
}
}
void
@@ -238,6 +261,15 @@ AMDGPUDevice::writeMMIO(PacketPtr pkt, Addr offset)
DPRINTF(AMDGPUDevice, "Wrote MMIO %#lx\n", offset);
switch (aperture) {
/* Write a register to the first System DMA. */
case SDMA0_BASE:
sdma0->writeMMIO(pkt, aperture_offset >> SDMA_OFFSET_SHIFT);
break;
/* Write a register to the second System DMA. */
case SDMA1_BASE:
sdma1->writeMMIO(pkt, aperture_offset >> SDMA_OFFSET_SHIFT);
break;
/* Write a register to the interrupt handler. */
case IH_BASE:
deviceIH->writeMMIO(pkt, aperture_offset >> IH_OFFSET_SHIFT);
break;