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arch-arm, dev-arm: Implement EL2 Secure Physical Timer

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Change-Id: I052f72695e670fad492079ab912268d05c797100
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58111
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2022-03-15 20:46:56 +00:00
parent f10fe51e18
commit e6797303c4
5 changed files with 53 additions and 13 deletions
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34
src/dev/arm/generic_timer.cc
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@@ -499,7 +499,8 @@ GenericTimer::createTimers(unsigned cpus)
p.int_el1_phys->get(tc),
p.int_el1_virt->get(tc),
p.int_el2_ns_phys->get(tc),
p.int_el2_ns_virt->get(tc)));
p.int_el2_ns_virt->get(tc),
p.int_el2_s_phys->get(tc)));
}
}
@@ -661,6 +662,19 @@ GenericTimer::setMiscReg(int reg, unsigned cpu, RegVal val)
core.virtNsEL2.setTimerValue(val);
return;
// EL2 Secure physical timer
case MISCREG_CNTHPS_CTL_EL2:
core.physSEL2.setControl(val);
return;
case MISCREG_CNTHPS_CVAL_EL2:
core.physSEL2.setCompareValue(val);
return;
case MISCREG_CNTHPS_TVAL_EL2:
core.physSEL2.setTimerValue(val);
return;
default:
warn("Writing to unknown register: %s\n", miscRegName[reg]);
return;
@@ -758,6 +772,16 @@ GenericTimer::readMiscReg(int reg, unsigned cpu)
case MISCREG_CNTHV_TVAL_EL2:
return core.virtNsEL2.timerValue();
// EL2 Secure physical timer
case MISCREG_CNTHPS_CTL_EL2:
return core.physSEL2.control();
case MISCREG_CNTHPS_CVAL_EL2:
return core.physSEL2.compareValue();
case MISCREG_CNTHPS_TVAL_EL2:
return core.physSEL2.timerValue();
default:
warn("Reading from unknown register: %s\n", miscRegName[reg]);
return 0;
@@ -768,7 +792,7 @@ GenericTimer::CoreTimers::CoreTimers(GenericTimer &_parent,
ArmSystem &system, unsigned cpu,
ArmInterruptPin *irq_el3_phys, ArmInterruptPin *irq_el1_phys,
ArmInterruptPin *irq_el1_virt, ArmInterruptPin *irq_el2_ns_phys,
ArmInterruptPin *irq_el2_ns_virt)
ArmInterruptPin *irq_el2_ns_virt, ArmInterruptPin *irq_el2_s_phys)
: parent(_parent),
cntfrq(parent.params().cntfrq),
cntkctl(0), cnthctl(0),
@@ -778,6 +802,7 @@ GenericTimer::CoreTimers::CoreTimers(GenericTimer &_parent,
irqVirtEL1(irq_el1_virt),
irqPhysNsEL2(irq_el2_ns_phys),
irqVirtNsEL2(irq_el2_ns_virt),
irqPhysSEL2(irq_el2_s_phys),
physEL3(csprintf("%s.el3_phys_timer%d", parent.name(), cpu),
system, parent, parent.systemCounter,
irq_el3_phys),
@@ -793,6 +818,9 @@ GenericTimer::CoreTimers::CoreTimers(GenericTimer &_parent,
virtNsEL2(csprintf("%s.el2_ns_virt_timer%d", parent.name(), cpu),
system, parent, parent.systemCounter,
irq_el2_ns_virt),
physSEL2(csprintf("%s.el2_s_phys_timer%d", parent.name(), cpu),
system, parent, parent.systemCounter,
irq_el2_s_phys),
physEvStream{
EventFunctionWrapper([this]{ physEventStreamCallback(); },
csprintf("%s.phys_event_gen%d", parent.name(), cpu)), 0, 0
@@ -870,6 +898,7 @@ GenericTimer::CoreTimers::serialize(CheckpointOut &cp) const
virtEL1.serializeSection(cp, "virt_el1_timer");
physNsEL2.serializeSection(cp, "phys_ns_el2_timer");
virtNsEL2.serializeSection(cp, "virt_ns_el2_timer");
physSEL2.serializeSection(cp, "phys_s_el2_timer");
}
void
@@ -904,6 +933,7 @@ GenericTimer::CoreTimers::unserialize(CheckpointIn &cp)
virtEL1.unserializeSection(cp, "virt_el1_timer");
physNsEL2.unserializeSection(cp, "phys_ns_el2_timer");
virtNsEL2.unserializeSection(cp, "virt_ns_el2_timer");
physSEL2.unserializeSection(cp, "phys_s_el2_timer");
}
void