diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index e101d93fa8..908641c49f 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -197,6 +197,8 @@ class ArmStaticInst : public StaticInst
         pcState.advance();
     }
 
+    uint64_t getEMI() const override { return machInst; }
+
     std::string generateDisassembly(
             Addr pc, const Loader::SymbolTable *symtab) const override;
 
diff --git a/src/cpu/minor/func_unit.cc b/src/cpu/minor/func_unit.cc
index 58f3a1e721..8c5e3a6bb4 100644
--- a/src/cpu/minor/func_unit.cc
+++ b/src/cpu/minor/func_unit.cc
@@ -171,13 +171,12 @@ FUPipeline::advance()
 MinorFUTiming *
 FUPipeline::findTiming(const StaticInstPtr &inst)
 {
-#if THE_ISA == ARM_ISA
-    /* This should work for any ISA with a POD mach_inst */
-    TheISA::ExtMachInst mach_inst = inst->machInst;
-#else
-    /* Just allow extra decode based on op classes */
-    uint64_t mach_inst = 0;
-#endif
+    /*
+     * This will only work on ISAs with an instruction format with a fixed size
+     * which can be categorized using bit masks. This is really only supported
+     * on ARM and is a bit of a hack.
+     */
+    uint64_t mach_inst = inst->getEMI();
 
     const std::vector<MinorFUTiming *> &timings =
         description.timings;
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 09f171f5ba..b2cd50851b 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -258,6 +258,8 @@ class StaticInst : public RefCounted, public StaticInstFlags
     /// The binary machine instruction.
     const TheISA::ExtMachInst machInst;
 
+    virtual uint64_t getEMI() const { return 0; }
+
   protected:
 
     /**