From e5bdc760e32045a75f9213e3cab8f164f0d6ce40 Mon Sep 17 00:00:00 2001
From: Arteen Abrishami <114886331+arteen1000@users.noreply.github.com>
Date: Fri, 12 Jan 2024 10:02:29 -0800
Subject: [PATCH] mem-ruby: allow comparison of int and Addr in SLICC (#701)

allow easy isolation of specific addresses in coherence protocols.
useful for debugging.

Change-Id: I93e07956b8e29837219d328dacfbd5c6067c1a62
---
 src/mem/slicc/ast/OperatorExprAST.py | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/mem/slicc/ast/OperatorExprAST.py b/src/mem/slicc/ast/OperatorExprAST.py
index 87417b50ea..c024c3071f 100644
--- a/src/mem/slicc/ast/OperatorExprAST.py
+++ b/src/mem/slicc/ast/OperatorExprAST.py
@@ -62,7 +62,15 @@ class InfixOperatorExprAST(ExprAST):
         # Figure out what the input and output types should be
         if self.op in ("==", "!=", ">=", "<=", ">", "<"):
             output = "bool"
-            if ltype != rtype:
+
+            if (
+                str(ltype) == "Addr"
+                and str(rtype) == "int"
+                or str(ltype) == "int"
+                and str(rtype) == "Addr"
+            ):
+                pass
+            elif ltype != rtype:
                 self.error(
                     "Type mismatch: left and right operands of "
                     + "operator '%s' must be the same type. "