diff --git a/configs/example/components-library/riscv_fs.py b/configs/example/components-library/riscv_fs.py index f46e36bf07..807e35f4c4 100644 --- a/configs/example/components-library/riscv_fs.py +++ b/configs/example/components-library/riscv_fs.py @@ -38,12 +38,12 @@ Characteristics import m5 from m5.objects import Root -from components_library.runtime import get_runtime_isa -from components_library.boards.riscv_board import RiscvBoard -from components_library.memory.single_channel import SingleChannelDDR3_1600 -from components_library.processors.simple_processor import SimpleProcessor -from components_library.processors.cpu_types import CPUTypes -from components_library.isas import ISA +from gem5.runtime import get_runtime_isa +from gem5.components.boards.riscv_board import RiscvBoard +from gem5.components.memory.single_channel import SingleChannelDDR3_1600 +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.components.processors.cpu_types import CPUTypes +from gem5.isas import ISA import os import subprocess @@ -54,11 +54,11 @@ import shutil if get_runtime_isa() != ISA.RISCV: raise EnvironmentError("The riscv_fs.py should be run with RISCV ISA.") -from components_library.cachehierarchies.classic.\ - private_l1_private_l2_cache_hierarchy import ( - PrivateL1PrivateL2CacheHierarchy, -) -from components_library.boards.riscv_board import RiscvBoard +from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy \ + import ( + PrivateL1PrivateL2CacheHierarchy, + ) +from gem5.boards.riscv_board import RiscvBoard # Setup the cache hierarchy. PrivateL1PrivateL2 and NoCache have been tested. cache_hierarchy = PrivateL1PrivateL2CacheHierarchy( diff --git a/src/python/SConscript b/src/python/SConscript index 548e6f581a..0d72f93554 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -28,167 +28,149 @@ Import('*') -PySource('components_library', 'components_library/__init__.py') -PySource('components_library', 'components_library/coherence_protocol.py') -PySource('components_library', 'components_library/isas.py') -PySource('components_library', 'components_library/runtime.py') -PySource('components_library.boards', 'components_library/boards/__init__.py') -PySource('components_library.boards', - 'components_library/boards/abstract_board.py') -PySource('components_library.boards', - 'components_library/boards/mem_mode.py') -PySource('components_library.boards', - 'components_library/boards/riscv_board.py') -PySource('components_library.boards', - 'components_library/boards/simple_board.py') -PySource('components_library.boards', - 'components_library/boards/test_board.py') -PySource('components_library.boards', 'components_library/boards/x86_board.py') -PySource('components_library.cachehierarchies', - 'components_library/cachehierarchies/__init__.py') -PySource('components_library.cachehierarchies', - 'components_library/cachehierarchies/abstract_cache_hierarchy.py') -PySource('components_library.cachehierarchies', - 'components_library/cachehierarchies/' - 'abstract_two_level_cache_hierarchy.py') -PySource('components_library.cachehierarchies.classic', - 'components_library/cachehierarchies/classic/__init__.py') -PySource('components_library.cachehierarchies.classic', - 'components_library/cachehierarchies/classic/' +PySource('gem5', 'gem5/__init__.py') +PySource('gem5', 'gem5/coherence_protocol.py') +PySource('gem5', 'gem5/isas.py') +PySource('gem5', 'gem5/runtime.py') +PySource('gem5.components', 'gem5/components/__init__.py') +PySource('gem5.components.boards', 'gem5/components/boards/__init__.py') +PySource('gem5.components.boards', 'gem5/components/boards/abstract_board.py') +PySource('gem5.components.boards', 'gem5/components/boards/mem_mode.py') +PySource('gem5.components.boards', 'gem5/components/boards/riscv_board.py') +PySource('gem5.components.boards', 'gem5/components/boards/simple_board.py') +PySource('gem5.components.boards', 'gem5/components/boards/test_board.py') +PySource('gem5.components.boards', 'gem5/components/boards/x86_board.py') +PySource('gem5.components.cachehierarchies', + 'gem5/components/cachehierarchies/__init__.py') +PySource('gem5.components.cachehierarchies', + 'gem5/components/cachehierarchies/abstract_cache_hierarchy.py') +PySource('gem5.components.cachehierarchies', + 'gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py') +PySource('gem5.components.cachehierarchies.classic', + 'gem5/components/cachehierarchies/classic/__init__.py') +PySource('gem5.components.cachehierarchies.classic', + 'gem5/components/cachehierarchies/classic/' 'abstract_classic_cache_hierarchy.py') -PySource('components_library.cachehierarchies.classic', - 'components_library/cachehierarchies/classic/no_cache.py') -PySource('components_library.cachehierarchies.classic', - 'components_library/cachehierarchies/classic/' - 'private_l1_cache_hierarchy.py') -PySource('components_library.cachehierarchies.classic', - 'components_library/cachehierarchies/classic/' +PySource('gem5.components.cachehierarchies.classic', + 'gem5/components/cachehierarchies/classic/no_cache.py') +PySource('gem5.components.cachehierarchies.classic', + 'gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py') +PySource('gem5.components.cachehierarchies.classic', + 'gem5/components/cachehierarchies/classic/' 'private_l1_private_l2_cache_hierarchy.py') -PySource('components_library.cachehierarchies.classic.caches', - 'components_library/cachehierarchies/classic/caches/__init__.py') -PySource('components_library.cachehierarchies.classic.caches', - 'components_library/cachehierarchies/classic/caches/l1dcache.py') -PySource('components_library.cachehierarchies.classic.caches', - 'components_library/cachehierarchies/classic/caches/l1icache.py') -PySource('components_library.cachehierarchies.classic.caches', - 'components_library/cachehierarchies/classic/caches/l2cache.py') -PySource('components_library.cachehierarchies.classic.caches', - 'components_library/cachehierarchies/classic/caches/mmu_cache.py') -PySource('components_library.cachehierarchies.ruby', - 'components_library/cachehierarchies/ruby/__init__.py') -PySource('components_library.cachehierarchies.ruby', - 'components_library/cachehierarchies/ruby/' - 'abstract_ruby_cache_hierarchy.py') -PySource('components_library.cachehierarchies.ruby', - 'components_library/cachehierarchies/ruby/' - 'mesi_two_level_cache_hierarchy.py') -PySource('components_library.cachehierarchies.ruby', - 'components_library/cachehierarchies/ruby/mi_example_cache_hierarchy.py') -PySource('components_library.cachehierarchies.ruby.caches', - 'components_library/cachehierarchies/ruby/caches/__init__.py') -PySource('components_library.cachehierarchies.ruby.caches', - 'components_library/cachehierarchies/ruby/caches/abstract_directory.py') -PySource('components_library.cachehierarchies.ruby.caches', - 'components_library/cachehierarchies/ruby/caches/' - 'abstract_dma_controller.py') -PySource('components_library.cachehierarchies.ruby.caches', - 'components_library/cachehierarchies/ruby/caches/abstract_l1_cache.py') -PySource('components_library.cachehierarchies.ruby.caches', - 'components_library/cachehierarchies/ruby/caches/abstract_l2_cache.py') -PySource('components_library.cachehierarchies.ruby.caches.mesi_two_level', - 'components_library/cachehierarchies/ruby/caches/mesi_two_level/' - '__init__.py') -PySource('components_library.cachehierarchies.ruby.caches.mesi_two_level', - 'components_library/cachehierarchies/ruby/caches/mesi_two_level/' - 'directory.py') -PySource('components_library.cachehierarchies.ruby.caches.mesi_two_level', - 'components_library/cachehierarchies/ruby/caches/mesi_two_level/' +PySource('gem5.components.cachehierarchies.classic.caches', + 'gem5/components/cachehierarchies/classic/caches/__init__.py') +PySource('gem5.components.cachehierarchies.classic.caches', + 'gem5/components/cachehierarchies/classic/caches/l1dcache.py') +PySource('gem5.components.cachehierarchies.classic.caches', + 'gem5/components/cachehierarchies/classic/caches/l1icache.py') +PySource('gem5.components.cachehierarchies.classic.caches', + 'gem5/components/cachehierarchies/classic/caches/l2cache.py') +PySource('gem5.components.cachehierarchies.classic.caches', + 'gem5/components/cachehierarchies/classic/caches/mmu_cache.py') +PySource('gem5.components.cachehierarchies.ruby', + 'gem5/components/cachehierarchies/ruby/__init__.py') +PySource('gem5.components.cachehierarchies.ruby', + 'gem5/components/cachehierarchies/ruby/abstract_ruby_cache_hierarchy.py') +PySource('gem5.components.cachehierarchies.ruby', + 'gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py') +PySource('gem5.components.cachehierarchies.ruby', + 'gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py') +PySource('gem5.components.cachehierarchies.ruby.caches', + 'gem5/components/cachehierarchies/ruby/caches/__init__.py') +PySource('gem5.components.cachehierarchies.ruby.caches', + 'gem5/components/cachehierarchies/ruby/caches/abstract_directory.py') +PySource('gem5.components.cachehierarchies.ruby.caches', + 'gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py') +PySource('gem5.components.cachehierarchies.ruby.caches', + 'gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py') +PySource('gem5.components.cachehierarchies.ruby.caches', + 'gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py') +PySource('gem5.components.cachehierarchies.ruby.caches.mesi_two_level', + 'gem5/components/cachehierarchies/ruby/caches/mesi_two_level/__init__.py') +PySource('gem5.components.cachehierarchies.ruby.caches.mesi_two_level', + 'gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py') +PySource('gem5.components.cachehierarchies.ruby.caches.mesi_two_level', + 'gem5/components/cachehierarchies/ruby/caches/mesi_two_level/' 'dma_controller.py') -PySource('components_library.cachehierarchies.ruby.caches.mesi_two_level', - 'components_library/cachehierarchies/ruby/caches/mesi_two_level/' - 'l1_cache.py') -PySource('components_library.cachehierarchies.ruby.caches.mesi_two_level', - 'components_library/cachehierarchies/ruby/caches/mesi_two_level/' - 'l2_cache.py') -PySource('components_library.cachehierarchies.ruby.caches.mi_example', - 'components_library/cachehierarchies/ruby/caches/mi_example/__init__.py') -PySource('components_library.cachehierarchies.ruby.caches.mi_example', - 'components_library/cachehierarchies/ruby/caches/mi_example/directory.py') -PySource('components_library.cachehierarchies.ruby.caches.mi_example', - 'components_library/cachehierarchies/ruby/caches/mi_example/' +PySource('gem5.components.cachehierarchies.ruby.caches.mesi_two_level', + 'gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py') +PySource('gem5.components.cachehierarchies.ruby.caches.mesi_two_level', + 'gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py') +PySource('gem5.components.cachehierarchies.ruby.caches.mi_example', + 'gem5/components/cachehierarchies/ruby/caches/mi_example/__init__.py') +PySource('gem5.components.cachehierarchies.ruby.caches.mi_example', + 'gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py') +PySource('gem5.components.cachehierarchies.ruby.caches.mi_example', + 'gem5/components/cachehierarchies/ruby/caches/mi_example/' 'dma_controller.py') -PySource('components_library.cachehierarchies.ruby.caches.mi_example', - 'components_library/cachehierarchies/ruby/caches/mi_example/l1_cache.py') -PySource('components_library.cachehierarchies.ruby.topologies', - 'components_library/cachehierarchies/ruby/topologies/__init__.py') -PySource('components_library.cachehierarchies.ruby.topologies', - 'components_library/cachehierarchies/ruby/topologies/simple_pt2pt.py') -PySource('components_library.memory', 'components_library/memory/__init__.py') -PySource('components_library.memory', - 'components_library/memory/abstract_memory_system.py') -PySource('components_library.memory', 'components_library/memory/dramsim_3.py') -PySource('components_library.memory', - 'components_library/memory/single_channel.py') -PySource('components_library.memory.dram_interfaces', - 'components_library/memory/dram_interfaces/__init__.py') -PySource('components_library.memory.dram_interfaces', - 'components_library/memory/dram_interfaces/ddr3.py') -PySource('components_library.memory.dram_interfaces', - 'components_library/memory/dram_interfaces/ddr4.py') -PySource('components_library.memory.dram_interfaces', - 'components_library/memory/dram_interfaces/gddr.py') -PySource('components_library.memory.dram_interfaces', - 'components_library/memory/dram_interfaces/hbm.py') -PySource('components_library.memory.dram_interfaces', - 'components_library/memory/dram_interfaces/hmc.py') -PySource('components_library.memory.dram_interfaces', - 'components_library/memory/dram_interfaces/lpddr2.py') -PySource('components_library.memory.dram_interfaces', - 'components_library/memory/dram_interfaces/lpddr3.py') -PySource('components_library.memory.dram_interfaces', - 'components_library/memory/dram_interfaces/lpddr5.py') -PySource('components_library.memory.dram_interfaces', - 'components_library/memory/dram_interfaces/wideio.py') -PySource('components_library.processors', - 'components_library/processors/__init__.py') -PySource('components_library.processors', - 'components_library/processors/abstract_core.py') -PySource('components_library.processors', - 'components_library/processors/abstract_generator_core.py') -PySource('components_library.processors', - 'components_library/processors/abstract_processor.py') -PySource('components_library.processors', - 'components_library/processors/complex_generator_core.py') -PySource('components_library.processors', - 'components_library/processors/complex_generator.py') -PySource('components_library.processors', - 'components_library/processors/cpu_types.py') -PySource('components_library.processors', - 'components_library/processors/linear_generator_core.py') -PySource('components_library.processors', - 'components_library/processors/linear_generator.py') -PySource('components_library.processors', - 'components_library/processors/random_generator_core.py') -PySource('components_library.processors', - 'components_library/processors/random_generator.py') -PySource('components_library.processors', - 'components_library/processors/simple_core.py') -PySource('components_library.processors', - 'components_library/processors/simple_processor.py') -PySource('components_library.processors', - 'components_library/processors/simple_switchable_processor.py') -PySource('components_library.processors', - 'components_library/processors/switchable_processor.py') -PySource('components_library.resources', - 'components_library/resources/__init__.py') -PySource('components_library.resources', - 'components_library/resources/downloader.py') -PySource('components_library.resources', - 'components_library/resources/resource.py') -PySource('components_library.utils', 'components_library/utils/__init__.py') -PySource('components_library.utils', 'components_library/utils/filelock.py') -PySource('components_library.utils', 'components_library/utils/override.py') -PySource('components_library.utils', 'components_library/utils/requires.py') +PySource('gem5.components.cachehierarchies.ruby.caches.mi_example', + 'gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py') +PySource('gem5.components.cachehierarchies.ruby.topologies', + 'gem5/components/cachehierarchies/ruby/topologies/__init__.py') +PySource('gem5.components.cachehierarchies.ruby.topologies', + 'gem5/components/cachehierarchies/ruby/topologies/simple_pt2pt.py') +PySource('gem5.components.memory', 'gem5/components/memory/__init__.py') +PySource('gem5.components.memory', 'gem5/components/memory/abstract_memory_system.py') +PySource('gem5.components.memory', 'gem5/components/memory/dramsim_3.py') +PySource('gem5.components.memory', 'gem5/components/memory/single_channel.py') +PySource('gem5.components.memory.dram_interfaces', + 'gem5/components/memory/dram_interfaces/__init__.py') +PySource('gem5.components.memory.dram_interfaces', + 'gem5/components/memory/dram_interfaces/ddr3.py') +PySource('gem5.components.memory.dram_interfaces', + 'gem5/components/memory/dram_interfaces/ddr4.py') +PySource('gem5.components.memory.dram_interfaces', + 'gem5/components/memory/dram_interfaces/gddr.py') +PySource('gem5.components.memory.dram_interfaces', + 'gem5/components/memory/dram_interfaces/hbm.py') +PySource('gem5.components.memory.dram_interfaces', + 'gem5/components/memory/dram_interfaces/hmc.py') +PySource('gem5.components.memory.dram_interfaces', + 'gem5/components/memory/dram_interfaces/lpddr2.py') +PySource('gem5.components.memory.dram_interfaces', + 'gem5/components/memory/dram_interfaces/lpddr3.py') +PySource('gem5.components.memory.dram_interfaces', +'gem5/components/memory/dram_interfaces/lpddr5.py') +PySource('gem5.components.memory.dram_interfaces', + 'gem5/components/memory/dram_interfaces/wideio.py') +PySource('gem5.components.processors', + 'gem5/components/processors/__init__.py') +PySource('gem5.components.processors', + 'gem5/components/processors/abstract_core.py') +PySource('gem5.components.processors', + 'gem5/components/processors/abstract_generator_core.py') +PySource('gem5.components.processors', + 'gem5/components/processors/abstract_processor.py') +PySource('gem5.components.processors', + 'gem5/components/processors/complex_generator_core.py') +PySource('gem5.components.processors', + 'gem5/components/processors/complex_generator.py') +PySource('gem5.components.processors', + 'gem5/components/processors/cpu_types.py') +PySource('gem5.components.processors', + 'gem5/components/processors/linear_generator_core.py') +PySource('gem5.components.processors', + 'gem5/components/processors/linear_generator.py') +PySource('gem5.components.processors', + 'gem5/components/processors/random_generator_core.py') +PySource('gem5.components.processors', + 'gem5/components/processors/random_generator.py') +PySource('gem5.components.processors', + 'gem5/components/processors/simple_core.py') +PySource('gem5.components.processors', + 'gem5/components/processors/simple_processor.py') +PySource('gem5.components.processors', + 'gem5/components/processors/simple_switchable_processor.py') +PySource('gem5.components.processors', + 'gem5/components/processors/switchable_processor.py') +PySource('gem5.resources', 'gem5/resources/__init__.py') +PySource('gem5.resources', 'gem5/resources/downloader.py') +PySource('gem5.resources', 'gem5/resources/resource.py') +PySource('gem5.utils', 'gem5/utils/__init__.py') +PySource('gem5.utils', 'gem5/utils/filelock.py') +PySource('gem5.utils', 'gem5/utils/override.py') +PySource('gem5.utils', 'gem5/utils/requires.py') PySource('', 'importer.py') PySource('m5', 'm5/__init__.py') diff --git a/src/python/components_library/README.md b/src/python/gem5/README.md similarity index 100% rename from src/python/components_library/README.md rename to src/python/gem5/README.md diff --git a/src/python/components_library/__init__.py b/src/python/gem5/__init__.py similarity index 100% rename from src/python/components_library/__init__.py rename to src/python/gem5/__init__.py diff --git a/src/python/components_library/coherence_protocol.py b/src/python/gem5/coherence_protocol.py similarity index 100% rename from src/python/components_library/coherence_protocol.py rename to src/python/gem5/coherence_protocol.py diff --git a/src/python/components_library/boards/__init__.py b/src/python/gem5/components/__init__.py similarity index 100% rename from src/python/components_library/boards/__init__.py rename to src/python/gem5/components/__init__.py diff --git a/src/python/components_library/cachehierarchies/__init__.py b/src/python/gem5/components/boards/__init__.py similarity index 100% rename from src/python/components_library/cachehierarchies/__init__.py rename to src/python/gem5/components/boards/__init__.py diff --git a/src/python/components_library/boards/abstract_board.py b/src/python/gem5/components/boards/abstract_board.py similarity index 100% rename from src/python/components_library/boards/abstract_board.py rename to src/python/gem5/components/boards/abstract_board.py diff --git a/src/python/components_library/boards/mem_mode.py b/src/python/gem5/components/boards/mem_mode.py similarity index 100% rename from src/python/components_library/boards/mem_mode.py rename to src/python/gem5/components/boards/mem_mode.py diff --git a/src/python/components_library/boards/riscv_board.py b/src/python/gem5/components/boards/riscv_board.py similarity index 99% rename from src/python/components_library/boards/riscv_board.py rename to src/python/gem5/components/boards/riscv_board.py index 97e32f02d5..dc8f7996a0 100644 --- a/src/python/components_library/boards/riscv_board.py +++ b/src/python/gem5/components/boards/riscv_board.py @@ -27,14 +27,14 @@ import os from typing import Optional -from ..utils.override import overrides +from ...utils.override import overrides from .simple_board import SimpleBoard from .abstract_board import AbstractBoard from ..processors.abstract_processor import AbstractProcessor from ..memory.abstract_memory_system import AbstractMemorySystem from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy -from ..isas import ISA -from ..runtime import get_runtime_isa +from ...isas import ISA +from ...runtime import get_runtime_isa import m5 diff --git a/src/python/components_library/boards/simple_board.py b/src/python/gem5/components/boards/simple_board.py similarity index 98% rename from src/python/components_library/boards/simple_board.py rename to src/python/gem5/components/boards/simple_board.py index 0ff9b79ef4..b52bc7c88f 100644 --- a/src/python/components_library/boards/simple_board.py +++ b/src/python/gem5/components/boards/simple_board.py @@ -24,7 +24,7 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ..resources.resource import AbstractResource +from ...resources.resource import AbstractResource from m5.objects import ( AddrRange, SrcClockDomain, @@ -41,7 +41,7 @@ from .mem_mode import MemMode, mem_mode_to_string from ..processors.abstract_processor import AbstractProcessor from ..memory.abstract_memory_system import AbstractMemorySystem from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy -from ..utils.override import overrides +from ...utils.override import overrides from typing import List diff --git a/src/python/components_library/boards/test_board.py b/src/python/gem5/components/boards/test_board.py similarity index 99% rename from src/python/components_library/boards/test_board.py rename to src/python/gem5/components/boards/test_board.py index bbfad49ac3..4bcefb1bb7 100644 --- a/src/python/components_library/boards/test_board.py +++ b/src/python/gem5/components/boards/test_board.py @@ -34,7 +34,7 @@ from m5.objects import ( ) from .mem_mode import MemMode, mem_mode_to_string -from ..utils.override import overrides +from ...utils.override import overrides from .abstract_board import AbstractBoard from ..processors.abstract_processor import AbstractProcessor from ..memory.abstract_memory_system import AbstractMemorySystem diff --git a/src/python/components_library/boards/x86_board.py b/src/python/gem5/components/boards/x86_board.py similarity index 98% rename from src/python/components_library/boards/x86_board.py rename to src/python/gem5/components/boards/x86_board.py index f752037441..e766c3edbf 100644 --- a/src/python/components_library/boards/x86_board.py +++ b/src/python/gem5/components/boards/x86_board.py @@ -25,10 +25,10 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ..resources.resource import AbstractResource -from ..utils.override import overrides +from ...resources.resource import AbstractResource +from ...utils.override import overrides from .abstract_board import AbstractBoard -from ..isas import ISA +from ...isas import ISA import m5 from m5.objects import ( @@ -60,7 +60,7 @@ from .simple_board import SimpleBoard from ..processors.abstract_processor import AbstractProcessor from ..memory.abstract_memory_system import AbstractMemorySystem from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy -from ..utils.requires import requires +from ...utils.requires import requires import os from typing import List, Optional, Sequence diff --git a/src/python/components_library/cachehierarchies/classic/__init__.py b/src/python/gem5/components/cachehierarchies/__init__.py similarity index 100% rename from src/python/components_library/cachehierarchies/classic/__init__.py rename to src/python/gem5/components/cachehierarchies/__init__.py diff --git a/src/python/components_library/cachehierarchies/abstract_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py similarity index 100% rename from src/python/components_library/cachehierarchies/abstract_cache_hierarchy.py rename to src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py diff --git a/src/python/components_library/cachehierarchies/abstract_two_level_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py similarity index 100% rename from src/python/components_library/cachehierarchies/abstract_two_level_cache_hierarchy.py rename to src/python/gem5/components/cachehierarchies/abstract_two_level_cache_hierarchy.py diff --git a/src/python/components_library/cachehierarchies/classic/caches/__init__.py b/src/python/gem5/components/cachehierarchies/classic/__init__.py similarity index 100% rename from src/python/components_library/cachehierarchies/classic/caches/__init__.py rename to src/python/gem5/components/cachehierarchies/classic/__init__.py diff --git a/src/python/components_library/cachehierarchies/classic/abstract_classic_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/abstract_classic_cache_hierarchy.py similarity index 98% rename from src/python/components_library/cachehierarchies/classic/abstract_classic_cache_hierarchy.py rename to src/python/gem5/components/cachehierarchies/classic/abstract_classic_cache_hierarchy.py index cc0d46b9fa..c492bfd438 100644 --- a/src/python/components_library/cachehierarchies/classic/abstract_classic_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/abstract_classic_cache_hierarchy.py @@ -25,7 +25,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from abc import abstractmethod -from ...utils.override import overrides +from ....utils.override import overrides from ..abstract_cache_hierarchy import AbstractCacheHierarchy from m5.objects import Port diff --git a/src/python/components_library/cachehierarchies/ruby/__init__.py b/src/python/gem5/components/cachehierarchies/classic/caches/__init__.py similarity index 100% rename from src/python/components_library/cachehierarchies/ruby/__init__.py rename to src/python/gem5/components/cachehierarchies/classic/caches/__init__.py diff --git a/src/python/components_library/cachehierarchies/classic/caches/l1dcache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py similarity index 98% rename from src/python/components_library/cachehierarchies/classic/caches/l1dcache.py rename to src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py index 2f83905992..7346e7a58b 100644 --- a/src/python/components_library/cachehierarchies/classic/caches/l1dcache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py @@ -24,7 +24,7 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ....utils.override import * +from .....utils.override import * from m5.objects import Cache, BasePrefetcher, StridePrefetcher diff --git a/src/python/components_library/cachehierarchies/classic/caches/l1icache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py similarity index 98% rename from src/python/components_library/cachehierarchies/classic/caches/l1icache.py rename to src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py index 214de416cd..d1bf5aa98e 100644 --- a/src/python/components_library/cachehierarchies/classic/caches/l1icache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py @@ -28,7 +28,7 @@ from typing import Optional, Type from m5.objects import Cache, BasePrefetcher, StridePrefetcher -from ....utils.override import * +from .....utils.override import * class L1ICache(Cache): diff --git a/src/python/components_library/cachehierarchies/classic/caches/l2cache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py similarity index 98% rename from src/python/components_library/cachehierarchies/classic/caches/l2cache.py rename to src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py index bd48919ac1..f3d7c14c69 100644 --- a/src/python/components_library/cachehierarchies/classic/caches/l2cache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py @@ -24,7 +24,7 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ....utils.override import * +from .....utils.override import * from m5.objects import Cache, BasePrefetcher, StridePrefetcher diff --git a/src/python/components_library/cachehierarchies/classic/caches/mmu_cache.py b/src/python/gem5/components/cachehierarchies/classic/caches/mmu_cache.py similarity index 98% rename from src/python/components_library/cachehierarchies/classic/caches/mmu_cache.py rename to src/python/gem5/components/cachehierarchies/classic/caches/mmu_cache.py index 8c72674660..580cb4e966 100644 --- a/src/python/components_library/cachehierarchies/classic/caches/mmu_cache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/mmu_cache.py @@ -24,7 +24,7 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ....utils.override import * +from .....utils.override import * from m5.objects import Cache, BasePrefetcher, StridePrefetcher diff --git a/src/python/components_library/cachehierarchies/classic/no_cache.py b/src/python/gem5/components/cachehierarchies/classic/no_cache.py similarity index 98% rename from src/python/components_library/cachehierarchies/classic/no_cache.py rename to src/python/gem5/components/cachehierarchies/classic/no_cache.py index 83a2dc83f9..d4f519d629 100644 --- a/src/python/components_library/cachehierarchies/classic/no_cache.py +++ b/src/python/gem5/components/cachehierarchies/classic/no_cache.py @@ -27,14 +27,14 @@ from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy from ..abstract_cache_hierarchy import AbstractCacheHierarchy from ...boards.abstract_board import AbstractBoard -from ...isas import ISA -from ...runtime import get_runtime_isa +from ....isas import ISA +from ....runtime import get_runtime_isa from m5.objects import Bridge, BaseXBar, SystemXBar, BadAddr, Port from typing import Optional -from ...utils.override import * +from ....utils.override import * class NoCache(AbstractClassicCacheHierarchy): diff --git a/src/python/components_library/cachehierarchies/classic/private_l1_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py similarity index 98% rename from src/python/components_library/cachehierarchies/classic/private_l1_cache_hierarchy.py rename to src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py index 15a0160505..03150dabc7 100644 --- a/src/python/components_library/cachehierarchies/classic/private_l1_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py @@ -30,12 +30,12 @@ from .caches.l1dcache import L1DCache from .caches.l1icache import L1ICache from .caches.mmu_cache import MMUCache from ...boards.abstract_board import AbstractBoard -from ...isas import ISA -from ...runtime import get_runtime_isa +from ....isas import ISA +from ....runtime import get_runtime_isa from m5.objects import Cache, BaseXBar, SystemXBar, BadAddr, Port -from ...utils.override import * +from ....utils.override import * from typing import Optional diff --git a/src/python/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py similarity index 98% rename from src/python/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py rename to src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py index 6d9c6037a4..eb4dae18be 100644 --- a/src/python/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py @@ -32,12 +32,12 @@ from .caches.l1icache import L1ICache from .caches.l2cache import L2Cache from .caches.mmu_cache import MMUCache from ...boards.abstract_board import AbstractBoard -from ...isas import ISA -from ...runtime import get_runtime_isa +from ....isas import ISA +from ....runtime import get_runtime_isa from m5.objects import Cache, L2XBar, BaseXBar, SystemXBar, BadAddr, Port -from ...utils.override import * +from ....utils.override import * from typing import Optional diff --git a/src/python/components_library/cachehierarchies/ruby/caches/__init__.py b/src/python/gem5/components/cachehierarchies/ruby/__init__.py similarity index 100% rename from src/python/components_library/cachehierarchies/ruby/caches/__init__.py rename to src/python/gem5/components/cachehierarchies/ruby/__init__.py diff --git a/src/python/components_library/cachehierarchies/ruby/abstract_ruby_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/ruby/abstract_ruby_cache_hierarchy.py similarity index 97% rename from src/python/components_library/cachehierarchies/ruby/abstract_ruby_cache_hierarchy.py rename to src/python/gem5/components/cachehierarchies/ruby/abstract_ruby_cache_hierarchy.py index 679d1a7e14..2648a01bc2 100644 --- a/src/python/components_library/cachehierarchies/ruby/abstract_ruby_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/ruby/abstract_ruby_cache_hierarchy.py @@ -24,7 +24,7 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ...utils.override import overrides +from ....utils.override import overrides from ..abstract_cache_hierarchy import AbstractCacheHierarchy diff --git a/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/__init__.py b/src/python/gem5/components/cachehierarchies/ruby/caches/__init__.py similarity index 100% rename from src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/__init__.py rename to src/python/gem5/components/cachehierarchies/ruby/caches/__init__.py diff --git a/src/python/components_library/cachehierarchies/ruby/caches/abstract_directory.py b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py similarity index 100% rename from src/python/components_library/cachehierarchies/ruby/caches/abstract_directory.py rename to src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py diff --git a/src/python/components_library/cachehierarchies/ruby/caches/abstract_dma_controller.py b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py similarity index 100% rename from src/python/components_library/cachehierarchies/ruby/caches/abstract_dma_controller.py rename to src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py diff --git a/src/python/components_library/cachehierarchies/ruby/caches/abstract_l1_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py similarity index 99% rename from src/python/components_library/cachehierarchies/ruby/caches/abstract_l1_cache.py rename to src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py index e694194b87..ea1995e6b5 100644 --- a/src/python/components_library/cachehierarchies/ruby/caches/abstract_l1_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py @@ -25,7 +25,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from abc import abstractmethod -from ....isas import ISA +from .....isas import ISA from ....processors.cpu_types import CPUTypes from ....processors.abstract_core import AbstractCore diff --git a/src/python/components_library/cachehierarchies/ruby/caches/abstract_l2_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py similarity index 100% rename from src/python/components_library/cachehierarchies/ruby/caches/abstract_l2_cache.py rename to src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py diff --git a/src/python/components_library/cachehierarchies/ruby/caches/mi_example/__init__.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/__init__.py similarity index 100% rename from src/python/components_library/cachehierarchies/ruby/caches/mi_example/__init__.py rename to src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/__init__.py diff --git a/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/directory.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py similarity index 98% rename from src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/directory.py rename to src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py index 18257659e3..cb10fbc7bf 100644 --- a/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/directory.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py @@ -24,7 +24,7 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .....utils.override import overrides +from ......utils.override import overrides from ..abstract_directory import AbstractDirectory from m5.objects import ( diff --git a/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py similarity index 98% rename from src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py rename to src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py index c37d4efac3..0f8a7b03bd 100644 --- a/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py @@ -24,7 +24,7 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .....utils.override import overrides +from ......utils.override import overrides from ..abstract_dma_controller import AbstractDMAController from m5.objects import MessageBuffer diff --git a/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py similarity index 98% rename from src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py rename to src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py index ab04d47b3f..fce222b927 100644 --- a/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py @@ -25,9 +25,9 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from .....processors.abstract_core import AbstractCore -from .....isas import ISA +from ......isas import ISA from ..abstract_l1_cache import AbstractL1Cache -from .....utils.override import * +from ......utils.override import * from m5.objects import ( MessageBuffer, diff --git a/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py similarity index 98% rename from src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py rename to src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py index 43f675e9d6..323ea523a6 100644 --- a/src/python/components_library/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py @@ -25,7 +25,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from ..abstract_l2_cache import AbstractL2Cache -from .....utils.override import * +from ......utils.override import * from m5.objects import MessageBuffer, RubyCache diff --git a/src/python/components_library/cachehierarchies/ruby/topologies/__init__.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/__init__.py similarity index 100% rename from src/python/components_library/cachehierarchies/ruby/topologies/__init__.py rename to src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/__init__.py diff --git a/src/python/components_library/cachehierarchies/ruby/caches/mi_example/directory.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py similarity index 98% rename from src/python/components_library/cachehierarchies/ruby/caches/mi_example/directory.py rename to src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py index 8110c4f41c..5cb819b567 100644 --- a/src/python/components_library/cachehierarchies/ruby/caches/mi_example/directory.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py @@ -25,7 +25,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from ..abstract_directory import AbstractDirectory -from .....utils.override import overrides +from ......utils.override import overrides from m5.objects import ( diff --git a/src/python/components_library/cachehierarchies/ruby/caches/mi_example/dma_controller.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py similarity index 98% rename from src/python/components_library/cachehierarchies/ruby/caches/mi_example/dma_controller.py rename to src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py index cee9d648fb..14b89253eb 100644 --- a/src/python/components_library/cachehierarchies/ruby/caches/mi_example/dma_controller.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py @@ -25,7 +25,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from ..abstract_dma_controller import AbstractDMAController -from .....utils.override import overrides +from ......utils.override import overrides from m5.objects import MessageBuffer diff --git a/src/python/components_library/cachehierarchies/ruby/caches/mi_example/l1_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py similarity index 97% rename from src/python/components_library/cachehierarchies/ruby/caches/mi_example/l1_cache.py rename to src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py index 55f1d5ead7..ffd5425636 100644 --- a/src/python/components_library/cachehierarchies/ruby/caches/mi_example/l1_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py @@ -24,9 +24,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from .....utils.override import overrides +from ......utils.override import overrides from .....processors.abstract_core import AbstractCore -from .....isas import ISA +from ......isas import ISA from ..abstract_l1_cache import AbstractL1Cache from m5.objects import ( diff --git a/src/python/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py similarity index 97% rename from src/python/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py rename to src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py index 7bda49cb1c..d8c972ed06 100644 --- a/src/python/components_library/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py @@ -27,11 +27,11 @@ from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy from ..abstract_two_level_cache_hierarchy import AbstractTwoLevelCacheHierarchy -from ...coherence_protocol import CoherenceProtocol -from ...isas import ISA +from ....coherence_protocol import CoherenceProtocol +from ....isas import ISA from ...boards.abstract_board import AbstractBoard -from ...runtime import get_runtime_isa -from ...utils.requires import requires +from ....runtime import get_runtime_isa +from ....utils.requires import requires from .topologies.simple_pt2pt import SimplePt2Pt from .caches.mesi_two_level.l1_cache import L1Cache diff --git a/src/python/components_library/cachehierarchies/ruby/mi_example_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py similarity index 97% rename from src/python/components_library/cachehierarchies/ruby/mi_example_cache_hierarchy.py rename to src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py index c5f93bdbae..338d1c4db9 100644 --- a/src/python/components_library/cachehierarchies/ruby/mi_example_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py @@ -31,11 +31,11 @@ from .topologies.simple_pt2pt import SimplePt2Pt from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy from ..abstract_cache_hierarchy import AbstractCacheHierarchy from ...boards.abstract_board import AbstractBoard -from ...coherence_protocol import CoherenceProtocol -from ...isas import ISA -from ...utils.override import overrides -from ...runtime import get_runtime_isa -from ...utils.requires import requires +from ....coherence_protocol import CoherenceProtocol +from ....isas import ISA +from ....utils.override import overrides +from ....runtime import get_runtime_isa +from ....utils.requires import requires from m5.objects import ( diff --git a/src/python/components_library/memory/__init__.py b/src/python/gem5/components/cachehierarchies/ruby/topologies/__init__.py similarity index 100% rename from src/python/components_library/memory/__init__.py rename to src/python/gem5/components/cachehierarchies/ruby/topologies/__init__.py diff --git a/src/python/components_library/cachehierarchies/ruby/topologies/simple_pt2pt.py b/src/python/gem5/components/cachehierarchies/ruby/topologies/simple_pt2pt.py similarity index 100% rename from src/python/components_library/cachehierarchies/ruby/topologies/simple_pt2pt.py rename to src/python/gem5/components/cachehierarchies/ruby/topologies/simple_pt2pt.py diff --git a/src/python/components_library/memory/dram_interfaces/__init__.py b/src/python/gem5/components/memory/__init__.py similarity index 100% rename from src/python/components_library/memory/dram_interfaces/__init__.py rename to src/python/gem5/components/memory/__init__.py diff --git a/src/python/components_library/memory/abstract_memory_system.py b/src/python/gem5/components/memory/abstract_memory_system.py similarity index 100% rename from src/python/components_library/memory/abstract_memory_system.py rename to src/python/gem5/components/memory/abstract_memory_system.py diff --git a/src/python/components_library/processors/__init__.py b/src/python/gem5/components/memory/dram_interfaces/__init__.py similarity index 100% rename from src/python/components_library/processors/__init__.py rename to src/python/gem5/components/memory/dram_interfaces/__init__.py diff --git a/src/python/components_library/memory/dram_interfaces/ddr3.py b/src/python/gem5/components/memory/dram_interfaces/ddr3.py similarity index 100% rename from src/python/components_library/memory/dram_interfaces/ddr3.py rename to src/python/gem5/components/memory/dram_interfaces/ddr3.py diff --git a/src/python/components_library/memory/dram_interfaces/ddr4.py b/src/python/gem5/components/memory/dram_interfaces/ddr4.py similarity index 100% rename from src/python/components_library/memory/dram_interfaces/ddr4.py rename to src/python/gem5/components/memory/dram_interfaces/ddr4.py diff --git a/src/python/components_library/memory/dram_interfaces/gddr.py b/src/python/gem5/components/memory/dram_interfaces/gddr.py similarity index 100% rename from src/python/components_library/memory/dram_interfaces/gddr.py rename to src/python/gem5/components/memory/dram_interfaces/gddr.py diff --git a/src/python/components_library/memory/dram_interfaces/hbm.py b/src/python/gem5/components/memory/dram_interfaces/hbm.py similarity index 100% rename from src/python/components_library/memory/dram_interfaces/hbm.py rename to src/python/gem5/components/memory/dram_interfaces/hbm.py diff --git a/src/python/components_library/memory/dram_interfaces/hmc.py b/src/python/gem5/components/memory/dram_interfaces/hmc.py similarity index 100% rename from src/python/components_library/memory/dram_interfaces/hmc.py rename to src/python/gem5/components/memory/dram_interfaces/hmc.py diff --git a/src/python/components_library/memory/dram_interfaces/lpddr2.py b/src/python/gem5/components/memory/dram_interfaces/lpddr2.py similarity index 100% rename from src/python/components_library/memory/dram_interfaces/lpddr2.py rename to src/python/gem5/components/memory/dram_interfaces/lpddr2.py diff --git a/src/python/components_library/memory/dram_interfaces/lpddr3.py b/src/python/gem5/components/memory/dram_interfaces/lpddr3.py similarity index 100% rename from src/python/components_library/memory/dram_interfaces/lpddr3.py rename to src/python/gem5/components/memory/dram_interfaces/lpddr3.py diff --git a/src/python/components_library/memory/dram_interfaces/lpddr5.py b/src/python/gem5/components/memory/dram_interfaces/lpddr5.py similarity index 100% rename from src/python/components_library/memory/dram_interfaces/lpddr5.py rename to src/python/gem5/components/memory/dram_interfaces/lpddr5.py diff --git a/src/python/components_library/memory/dram_interfaces/wideio.py b/src/python/gem5/components/memory/dram_interfaces/wideio.py similarity index 100% rename from src/python/components_library/memory/dram_interfaces/wideio.py rename to src/python/gem5/components/memory/dram_interfaces/wideio.py diff --git a/src/python/components_library/memory/dramsim_3.py b/src/python/gem5/components/memory/dramsim_3.py similarity index 99% rename from src/python/components_library/memory/dramsim_3.py rename to src/python/gem5/components/memory/dramsim_3.py index b41935bec7..5e7ec12c65 100644 --- a/src/python/components_library/memory/dramsim_3.py +++ b/src/python/gem5/components/memory/dramsim_3.py @@ -5,7 +5,7 @@ import configparser from m5.objects import DRAMsim3, AddrRange, Port, MemCtrl from m5.util.convert import toMemorySize -from ..utils.override import overrides +from ...utils.override import overrides from ..boards.abstract_board import AbstractBoard from .abstract_memory_system import AbstractMemorySystem diff --git a/src/python/components_library/memory/single_channel.py b/src/python/gem5/components/memory/single_channel.py similarity index 99% rename from src/python/components_library/memory/single_channel.py rename to src/python/gem5/components/memory/single_channel.py index fcaab40a89..11a0b15caa 100644 --- a/src/python/components_library/memory/single_channel.py +++ b/src/python/gem5/components/memory/single_channel.py @@ -29,7 +29,7 @@ from ..boards.abstract_board import AbstractBoard from .abstract_memory_system import AbstractMemorySystem -from ..utils.override import overrides +from ...utils.override import overrides from m5.objects import AddrRange, DRAMInterface, MemCtrl, Port from m5.util.convert import toMemorySize diff --git a/src/python/components_library/resources/__init__.py b/src/python/gem5/components/processors/__init__.py similarity index 100% rename from src/python/components_library/resources/__init__.py rename to src/python/gem5/components/processors/__init__.py diff --git a/src/python/components_library/processors/abstract_core.py b/src/python/gem5/components/processors/abstract_core.py similarity index 99% rename from src/python/components_library/processors/abstract_core.py rename to src/python/gem5/components/processors/abstract_core.py index e3652686f8..0a58fdf9c9 100644 --- a/src/python/components_library/processors/abstract_core.py +++ b/src/python/gem5/components/processors/abstract_core.py @@ -27,7 +27,7 @@ from abc import ABCMeta, abstractmethod from typing import Optional from .cpu_types import CPUTypes -from ..utils.requires import requires +from ...utils.requires import requires from m5.objects import BaseMMU, Port, SubSystem diff --git a/src/python/components_library/processors/abstract_generator_core.py b/src/python/gem5/components/processors/abstract_generator_core.py similarity index 98% rename from src/python/components_library/processors/abstract_generator_core.py rename to src/python/gem5/components/processors/abstract_generator_core.py index 226dfa6c76..48049d852c 100644 --- a/src/python/components_library/processors/abstract_generator_core.py +++ b/src/python/gem5/components/processors/abstract_generator_core.py @@ -26,7 +26,7 @@ from m5.objects import Port, PyTrafficGen -from ..utils.override import overrides +from ...utils.override import overrides from .cpu_types import CPUTypes from .abstract_core import AbstractCore diff --git a/src/python/components_library/processors/abstract_processor.py b/src/python/gem5/components/processors/abstract_processor.py similarity index 100% rename from src/python/components_library/processors/abstract_processor.py rename to src/python/gem5/components/processors/abstract_processor.py diff --git a/src/python/components_library/processors/complex_generator.py b/src/python/gem5/components/processors/complex_generator.py similarity index 99% rename from src/python/components_library/processors/complex_generator.py rename to src/python/gem5/components/processors/complex_generator.py index 61b98917bc..418375c1a2 100644 --- a/src/python/components_library/processors/complex_generator.py +++ b/src/python/gem5/components/processors/complex_generator.py @@ -24,7 +24,7 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ..utils.override import overrides +from ...utils.override import overrides from ..boards.mem_mode import MemMode from .complex_generator_core import ComplexGeneratorCore diff --git a/src/python/components_library/processors/complex_generator_core.py b/src/python/gem5/components/processors/complex_generator_core.py similarity index 99% rename from src/python/components_library/processors/complex_generator_core.py rename to src/python/gem5/components/processors/complex_generator_core.py index 82272bc2f5..190631f7d4 100644 --- a/src/python/components_library/processors/complex_generator_core.py +++ b/src/python/gem5/components/processors/complex_generator_core.py @@ -31,7 +31,7 @@ from m5.objects import PyTrafficGen, Port from .abstract_core import AbstractCore from .abstract_generator_core import AbstractGeneratorCore -from ..utils.override import overrides +from ...utils.override import overrides from enum import Enum diff --git a/src/python/components_library/processors/cpu_types.py b/src/python/gem5/components/processors/cpu_types.py similarity index 100% rename from src/python/components_library/processors/cpu_types.py rename to src/python/gem5/components/processors/cpu_types.py diff --git a/src/python/components_library/processors/linear_generator.py b/src/python/gem5/components/processors/linear_generator.py similarity index 99% rename from src/python/components_library/processors/linear_generator.py rename to src/python/gem5/components/processors/linear_generator.py index 3e9bc501ca..d220450cbe 100644 --- a/src/python/components_library/processors/linear_generator.py +++ b/src/python/gem5/components/processors/linear_generator.py @@ -24,7 +24,7 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ..utils.override import overrides +from ...utils.override import overrides from ..boards.mem_mode import MemMode from .linear_generator_core import LinearGeneratorCore diff --git a/src/python/components_library/processors/linear_generator_core.py b/src/python/gem5/components/processors/linear_generator_core.py similarity index 99% rename from src/python/components_library/processors/linear_generator_core.py rename to src/python/gem5/components/processors/linear_generator_core.py index 010debe70b..8769c77908 100644 --- a/src/python/components_library/processors/linear_generator_core.py +++ b/src/python/gem5/components/processors/linear_generator_core.py @@ -31,7 +31,7 @@ from m5.objects import PyTrafficGen, Port, BaseTrafficGen from .abstract_core import AbstractCore from .abstract_generator_core import AbstractGeneratorCore -from ..utils.override import overrides +from ...utils.override import overrides from typing import Iterator diff --git a/src/python/components_library/processors/random_generator.py b/src/python/gem5/components/processors/random_generator.py similarity index 99% rename from src/python/components_library/processors/random_generator.py rename to src/python/gem5/components/processors/random_generator.py index 80eb763b85..df70f2c7f1 100644 --- a/src/python/components_library/processors/random_generator.py +++ b/src/python/gem5/components/processors/random_generator.py @@ -24,7 +24,7 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ..utils.override import overrides +from ...utils.override import overrides from ..boards.mem_mode import MemMode from .random_generator_core import RandomGeneratorCore diff --git a/src/python/components_library/processors/random_generator_core.py b/src/python/gem5/components/processors/random_generator_core.py similarity index 99% rename from src/python/components_library/processors/random_generator_core.py rename to src/python/gem5/components/processors/random_generator_core.py index 3fa5ebe5ca..e5865fc271 100644 --- a/src/python/components_library/processors/random_generator_core.py +++ b/src/python/gem5/components/processors/random_generator_core.py @@ -31,7 +31,7 @@ from m5.objects import PyTrafficGen, Port, BaseTrafficGen from .abstract_core import AbstractCore from .abstract_generator_core import AbstractGeneratorCore -from ..utils.override import overrides +from ...utils.override import overrides from typing import Iterator diff --git a/src/python/components_library/processors/simple_core.py b/src/python/gem5/components/processors/simple_core.py similarity index 97% rename from src/python/components_library/processors/simple_core.py rename to src/python/gem5/components/processors/simple_core.py index f502e68dbe..6c0d6a5ce4 100644 --- a/src/python/components_library/processors/simple_core.py +++ b/src/python/gem5/components/processors/simple_core.py @@ -25,12 +25,12 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from typing import Optional -from ..runtime import get_runtime_isa +from ...runtime import get_runtime_isa from ..processors.abstract_core import AbstractCore from .cpu_types import CPUTypes -from ..isas import ISA -from ..utils.override import overrides +from ...isas import ISA +from ...utils.override import overrides from m5.objects import ( BaseMMU, diff --git a/src/python/components_library/processors/simple_processor.py b/src/python/gem5/components/processors/simple_processor.py similarity index 98% rename from src/python/components_library/processors/simple_processor.py rename to src/python/gem5/components/processors/simple_processor.py index d2640349f5..8bc7f8b742 100644 --- a/src/python/components_library/processors/simple_processor.py +++ b/src/python/gem5/components/processors/simple_processor.py @@ -25,7 +25,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from ..utils.override import overrides +from ...utils.override import overrides from ..boards.mem_mode import MemMode from ..processors.simple_core import SimpleCore diff --git a/src/python/components_library/processors/simple_switchable_processor.py b/src/python/gem5/components/processors/simple_switchable_processor.py similarity index 99% rename from src/python/components_library/processors/simple_switchable_processor.py rename to src/python/gem5/components/processors/simple_switchable_processor.py index 9d69588dd9..3614aca475 100644 --- a/src/python/components_library/processors/simple_switchable_processor.py +++ b/src/python/gem5/components/processors/simple_switchable_processor.py @@ -30,7 +30,7 @@ from ..processors.simple_core import SimpleCore from ..processors.cpu_types import CPUTypes from .switchable_processor import SwitchableProcessor -from ..utils.override import * +from ...utils.override import * from m5.objects import KvmVM diff --git a/src/python/components_library/processors/switchable_processor.py b/src/python/gem5/components/processors/switchable_processor.py similarity index 99% rename from src/python/components_library/processors/switchable_processor.py rename to src/python/gem5/components/processors/switchable_processor.py index 772304b95f..dea281540a 100644 --- a/src/python/components_library/processors/switchable_processor.py +++ b/src/python/gem5/components/processors/switchable_processor.py @@ -35,7 +35,7 @@ from typing import Dict, Any, List from .abstract_processor import AbstractProcessor from ..boards.abstract_board import AbstractBoard -from ..utils.override import * +from ...utils.override import * class SwitchableProcessor(AbstractProcessor): diff --git a/src/python/components_library/isas.py b/src/python/gem5/isas.py similarity index 100% rename from src/python/components_library/isas.py rename to src/python/gem5/isas.py diff --git a/src/python/components_library/utils/__init__.py b/src/python/gem5/resources/__init__.py similarity index 100% rename from src/python/components_library/utils/__init__.py rename to src/python/gem5/resources/__init__.py diff --git a/src/python/components_library/resources/downloader.py b/src/python/gem5/resources/downloader.py similarity index 100% rename from src/python/components_library/resources/downloader.py rename to src/python/gem5/resources/downloader.py diff --git a/src/python/components_library/resources/resource.py b/src/python/gem5/resources/resource.py similarity index 100% rename from src/python/components_library/resources/resource.py rename to src/python/gem5/resources/resource.py diff --git a/src/python/components_library/runtime.py b/src/python/gem5/runtime.py similarity index 100% rename from src/python/components_library/runtime.py rename to src/python/gem5/runtime.py diff --git a/src/python/gem5/utils/__init__.py b/src/python/gem5/utils/__init__.py new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/python/components_library/utils/filelock.py b/src/python/gem5/utils/filelock.py similarity index 100% rename from src/python/components_library/utils/filelock.py rename to src/python/gem5/utils/filelock.py diff --git a/src/python/components_library/utils/override.py b/src/python/gem5/utils/override.py similarity index 100% rename from src/python/components_library/utils/override.py rename to src/python/gem5/utils/override.py diff --git a/src/python/components_library/utils/requires.py b/src/python/gem5/utils/requires.py similarity index 100% rename from src/python/components_library/utils/requires.py rename to src/python/gem5/utils/requires.py diff --git a/tests/gem5/configs/components-library/boot_exit_disk_run.py b/tests/gem5/configs/boot_exit_disk_run.py similarity index 90% rename from tests/gem5/configs/components-library/boot_exit_disk_run.py rename to tests/gem5/configs/boot_exit_disk_run.py index 015d84eba1..6c5488d9a7 100644 --- a/tests/gem5/configs/components-library/boot_exit_disk_run.py +++ b/tests/gem5/configs/boot_exit_disk_run.py @@ -31,18 +31,18 @@ This script will run a simple boot exit test. import m5 from m5.objects import Root -from components_library.runtime import ( +from gem5.runtime import ( get_runtime_coherence_protocol, get_runtime_isa, ) -from components_library.utils.requires import requires -from components_library.boards.x86_board import X86Board -from components_library.memory.single_channel import SingleChannelDDR3_1600 -from components_library.processors.simple_processor import SimpleProcessor -from components_library.processors.cpu_types import CPUTypes -from components_library.isas import ISA -from components_library.coherence_protocol import CoherenceProtocol -from components_library.resources.resource import Resource +from gem5.utils.requires import requires +from gem5.components.boards.x86_board import X86Board +from gem5.components.memory.single_channel import SingleChannelDDR3_1600 +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.components.processors.cpu_types import CPUTypes +from gem5.isas import ISA +from gem5.coherence_protocol import CoherenceProtocol +from gem5.resources.resource import Resource import argparse @@ -121,14 +121,14 @@ requires(isa_required=ISA.X86, cache_hierarchy = None if args.mem_system == "mi_example": - from components_library.cachehierarchies.ruby.\ + from gem5.components.cachehierarchies.ruby.\ mi_example_cache_hierarchy import ( MIExampleCacheHierarchy, ) cache_hierarchy = MIExampleCacheHierarchy(size="32kB", assoc=8) elif args.mem_system == "mesi_two_level": - from components_library.cachehierarchies.ruby.\ + from gem5.components.cachehierarchies.ruby.\ mesi_two_level_cache_hierarchy import ( MESITwoLevelCacheHierarchy, ) @@ -143,7 +143,7 @@ elif args.mem_system == "mesi_two_level": num_l2_banks=1, ) elif args.mem_system == "classic": - from components_library.cachehierarchies.classic.\ + from gem5.components.cachehierarchies.classic.\ private_l1_cache_hierarchy import ( PrivateL1CacheHierarchy, ) diff --git a/tests/gem5/configs/components-library/boot_kvm_switch_exit.py b/tests/gem5/configs/boot_kvm_switch_exit.py similarity index 90% rename from tests/gem5/configs/components-library/boot_kvm_switch_exit.py rename to tests/gem5/configs/boot_kvm_switch_exit.py index 28102d8b0b..eaf9032ba7 100644 --- a/tests/gem5/configs/components-library/boot_kvm_switch_exit.py +++ b/tests/gem5/configs/boot_kvm_switch_exit.py @@ -33,19 +33,19 @@ import argparse import m5 from m5.objects import Root -from components_library.boards.x86_board import X86Board -from components_library.coherence_protocol import CoherenceProtocol -from components_library.isas import ISA -from components_library.memory.single_channel import SingleChannelDDR3_1600 -from components_library.processors.cpu_types import CPUTypes -from components_library.processors.simple_switchable_processor import ( +from gem5.components.boards.x86_board import X86Board +from gem5.coherence_protocol import CoherenceProtocol +from gem5.isas import ISA +from gem5.components.memory.single_channel import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.processors.simple_switchable_processor import ( SimpleSwitchableProcessor, ) -from components_library.resources.resource import Resource -from components_library.runtime import ( +from gem5.resources.resource import Resource +from gem5.runtime import ( get_runtime_coherence_protocol, get_runtime_isa ) -from components_library.utils.requires import requires +from gem5.utils.requires import requires parser = argparse.ArgumentParser( description="A script to test switching cpus. This test boots" @@ -112,14 +112,14 @@ requires( cache_hierarchy = None if args.mem_system == "mi_example": - from components_library.cachehierarchies.ruby.\ + from gem5.components.cachehierarchies.ruby.\ mi_example_cache_hierarchy import ( MIExampleCacheHierarchy, ) cache_hierarchy = MIExampleCacheHierarchy(size="32kB", assoc=8) elif args.mem_system == "mesi_two_level": - from components_library.cachehierarchies.ruby.\ + from gem5.components.cachehierarchies.ruby.\ mesi_two_level_cache_hierarchy import ( MESITwoLevelCacheHierarchy, ) @@ -134,7 +134,7 @@ elif args.mem_system == "mesi_two_level": num_l2_banks=1, ) elif args.mem_system == "classic": - from components_library.cachehierarchies.classic.\ + from gem5.components.cachehierarchies.classic.\ private_l1_cache_hierarchy import ( PrivateL1CacheHierarchy, ) diff --git a/tests/gem5/configs/components-library/parsec_disk_run.py b/tests/gem5/configs/parsec_disk_run.py similarity index 94% rename from tests/gem5/configs/components-library/parsec_disk_run.py rename to tests/gem5/configs/parsec_disk_run.py index 31df0bf73c..c354cdffc1 100644 --- a/tests/gem5/configs/components-library/parsec_disk_run.py +++ b/tests/gem5/configs/parsec_disk_run.py @@ -40,19 +40,19 @@ import m5.ticks from m5.objects import Root -from components_library.resources.resource import Resource -from components_library.boards.x86_board import X86Board -from components_library.memory.single_channel import SingleChannelDDR3_1600 -from components_library.processors.simple_switchable_processor import ( +from gem5.components.resources.resource import Resource +from gem5.components.boards.x86_board import X86Board +from gem5.components.memory.single_channel import SingleChannelDDR3_1600 +from gem5.components.processors.simple_switchable_processor import ( SimpleSwitchableProcessor, ) -from components_library.processors.cpu_types import CPUTypes -from components_library.isas import ISA -from components_library.runtime import ( +from gem5.components.processors.cpu_types import CPUTypes +from gem5.isas import ISA +from gem5.runtime import ( get_runtime_isa, get_runtime_coherence_protocol, ) -from components_library.utils.requires import requires +from gem5.utils.requires import requires import time import argparse @@ -156,7 +156,7 @@ args = parser.parse_args() if args.mem_system == "classic": - from components_library.cachehierarchies.classic.\ + from gem5.components.cachehierarchies.classic.\ private_l1_private_l2_cache_hierarchy import ( PrivateL1PrivateL2CacheHierarchy, ) @@ -167,7 +167,7 @@ if args.mem_system == "classic": l2_size="256kB", ) elif args.mem_system == "mesi_two_level": - from components_library.cachehierarchies.ruby.\ + from gem5.components.cachehierarchies.ruby.\ mesi_two_level_cache_hierarchy import ( MESITwoLevelCacheHierarchy, ) diff --git a/tests/gem5/configs/components-library/simple_binary_run.py b/tests/gem5/configs/simple_binary_run.py similarity index 90% rename from tests/gem5/configs/components-library/simple_binary_run.py rename to tests/gem5/configs/simple_binary_run.py index 9ed889dd64..2c27ef7819 100644 --- a/tests/gem5/configs/components-library/simple_binary_run.py +++ b/tests/gem5/configs/simple_binary_run.py @@ -33,12 +33,12 @@ gem5 while still being functinal. import m5 from m5.objects import Root -from components_library.resources.resource import Resource -from components_library.boards.simple_board import SimpleBoard -from components_library.cachehierarchies.classic.no_cache import NoCache -from components_library.memory.single_channel import SingleChannelDDR3_1600 -from components_library.processors.simple_processor import SimpleProcessor -from components_library.processors.cpu_types import CPUTypes +from gem5.resources.resource import Resource +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.memory.single_channel import SingleChannelDDR3_1600 +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.components.processors.cpu_types import CPUTypes import argparse diff --git a/tests/gem5/configs/components-library/simple_traffic_run.py b/tests/gem5/configs/simple_traffic_run.py similarity index 92% rename from tests/gem5/configs/components-library/simple_traffic_run.py rename to tests/gem5/configs/simple_traffic_run.py index 4b2e99ac56..2541d90bcc 100644 --- a/tests/gem5/configs/components-library/simple_traffic_run.py +++ b/tests/gem5/configs/simple_traffic_run.py @@ -37,10 +37,10 @@ from m5.objects import Root import argparse import importlib -from components_library.boards.test_board import TestBoard -from components_library.cachehierarchies.classic.no_cache import NoCache -from components_library.memory.single_channel import * -from components_library.processors.complex_generator import ComplexGenerator +from gem5.components.boards.test_board import TestBoard +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.memory.single_channel import * +from gem5.components.processors.complex_generator import ComplexGenerator parser = argparse.ArgumentParser( description="A traffic generator that can be used to test a gem5 " diff --git a/tests/gem5/hello_se/test_hello_se.py b/tests/gem5/hello_se/test_hello_se.py index 4893c3e785..4d3fb225ef 100644 --- a/tests/gem5/hello_se/test_hello_se.py +++ b/tests/gem5/hello_se/test_hello_se.py @@ -104,7 +104,6 @@ def verify_config(isa, binary, cpu, hosts): "tests", "gem5", "configs", - "components-library", "simple_binary_run.py", ), config_args=[ diff --git a/tests/gem5/insttest_se/test.py b/tests/gem5/insttest_se/test.py index fb5c2fc8ac..0464a9e606 100644 --- a/tests/gem5/insttest_se/test.py +++ b/tests/gem5/insttest_se/test.py @@ -55,7 +55,6 @@ for isa in test_progs: "tests", "gem5", "configs", - "components-library", "simple_binary_run.py", ), config_args=[ diff --git a/tests/gem5/m5_util/test_exit.py b/tests/gem5/m5_util/test_exit.py index a70caecea6..8a8ffc7ec4 100644 --- a/tests/gem5/m5_util/test_exit.py +++ b/tests/gem5/m5_util/test_exit.py @@ -61,7 +61,6 @@ gem5_verify_config( "tests", "gem5", "configs", - "components-library", "simple_binary_run.py", ), config_args=[ diff --git a/tests/gem5/parsec-benchmarks/test_parsec.py b/tests/gem5/parsec-benchmarks/test_parsec.py index 8662605321..66b36871f9 100644 --- a/tests/gem5/parsec-benchmarks/test_parsec.py +++ b/tests/gem5/parsec-benchmarks/test_parsec.py @@ -73,7 +73,6 @@ def test_parsec( "tests", "gem5", "configs", - "components-library", "parsec_disk_run.py", ), config_args=[ diff --git a/tests/gem5/stats/test_hdf5.py b/tests/gem5/stats/test_hdf5.py index 6537e5cde4..ad730f3bec 100644 --- a/tests/gem5/stats/test_hdf5.py +++ b/tests/gem5/stats/test_hdf5.py @@ -80,7 +80,6 @@ if have_hdf5(): "tests", "gem5", "configs", - "components-library", "simple_binary_run.py", ), config_args=[ diff --git a/tests/gem5/traffic_gen/test_memory_traffic_gen.py b/tests/gem5/traffic_gen/test_memory_traffic_gen.py index f3743003c1..e761fb6ced 100644 --- a/tests/gem5/traffic_gen/test_memory_traffic_gen.py +++ b/tests/gem5/traffic_gen/test_memory_traffic_gen.py @@ -25,8 +25,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. """ -This tests the gem5 components library memory components with a simple traffic -generator. +This tests the gem5 memory components with a simple traffic generator. TODO: At present all the Single Channel memory components are tested. This should be expanded to included DRAMSIM3 memory systems. @@ -45,7 +44,6 @@ def test_memory(module: str, memory: str, *args) -> None: "tests", "gem5", "configs", - "components-library", "simple_traffic_run.py", ), config_args=[ @@ -60,25 +58,27 @@ def test_memory(module: str, memory: str, *args) -> None: test_memory( - "components_library.memory.single_channel", + "gem5.components.memory.single_channel", "SingleChannelDDR3_1600", "512MiB", ) test_memory( - "components_library.memory.single_channel", + "gem5.components.memory.single_channel", "SingleChannelDDR3_2133", "512MiB", ) test_memory( - "components_library.memory.single_channel", + "gem5.components.memory.single_channel", "SingleChannelDDR4_2400", "512MiB", ) test_memory( - "components_library.memory.single_channel", + "gem5.components.memory.single_channel", "SingleChannelLPDDR3_1600", "512MiB", ) test_memory( - "components_library.memory.single_channel", "SingleChannelHBM", "512MiB" + "gem5.components.memory.single_channel", + "SingleChannelHBM", + "512MiB" ) diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py b/tests/gem5/x86-boot-tests/test_linux_boot.py index 53af891c11..f1fba8f5c1 100644 --- a/tests/gem5/x86-boot-tests/test_linux_boot.py +++ b/tests/gem5/x86-boot-tests/test_linux_boot.py @@ -80,7 +80,6 @@ def test_boot( "tests", "gem5", "configs", - "components-library", "boot_exit_disk_run.py", ), config_args=[