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arch-arm: Remove _Xt postfix from TLBI instructions

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The Xt is not part of the architectural name of the register
and it was likely added with the introduction of extended
register (Xt) TLBIs in Armv8 to differentiate them with
the old Armv7 ones.

The use of _Xt was not consistent anyway: newer TLBIs were
already omitting it.

Change-Id: Ic805340ffa7b5770e3b75a71bfb76e055e651f8b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2023-12-14 14:45:03 +00:00
parent 594428f010
commit e333a77c12
5 changed files with 397 additions and 397 deletions
Download Patch File Download Diff File Expand all files Collapse all files

120
src/arch/arm/insts/misc64.cc
View File

@@ -380,7 +380,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
// AArch64 TLB Invalidate by VA, EL3
case MISCREG_TLBI_VAE3_Xt:
case MISCREG_TLBI_VAE3:
{
TLBIMVAA tlbiOp(EL3, true,
@@ -390,7 +390,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
// AArch64 TLB Invalidate by VA, Last Level, EL3
case MISCREG_TLBI_VALE3_Xt:
case MISCREG_TLBI_VALE3:
{
TLBIMVAA tlbiOp(EL3, true,
@@ -400,11 +400,11 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
// AArch64 TLB Invalidate by VA, EL3, Inner Shareable
case MISCREG_TLBI_VAE3IS_Xt:
case MISCREG_TLBI_VAE3IS:
// AArch64 TLB Invalidate by VA, EL3, Outer Shareable
// We are currently not distinguishing Inner and Outer domains.
// We therefore implement TLBIOS instructions as TLBIIS
case MISCREG_TLBI_VAE3OS_Xt:
case MISCREG_TLBI_VAE3OS:
{
TLBIMVAA tlbiOp(EL3, true,
static_cast<Addr>(bits(value, 43, 0)) << 12,
@@ -414,11 +414,11 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
// AArch64 TLB Invalidate by VA, Last Level, EL3, Inner Shareable
case MISCREG_TLBI_VALE3IS_Xt:
case MISCREG_TLBI_VALE3IS:
// AArch64 TLB Invalidate by VA, Last Level, EL3, Outer Shareable
// We are currently not distinguishing Inner and Outer domains.
// We therefore implement TLBIOS instructions as TLBIIS
case MISCREG_TLBI_VALE3OS_Xt:
case MISCREG_TLBI_VALE3OS:
{
TLBIMVAA tlbiOp(EL3, true,
static_cast<Addr>(bits(value, 43, 0)) << 12,
@@ -428,7 +428,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
// AArch64 TLB Invalidate by VA, EL2
case MISCREG_TLBI_VAE2_Xt:
case MISCREG_TLBI_VAE2:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
@@ -453,7 +453,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
// AArch64 TLB Invalidate by VA, Last Level, EL2
case MISCREG_TLBI_VALE2_Xt:
case MISCREG_TLBI_VALE2:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
@@ -478,11 +478,11 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
// AArch64 TLB Invalidate by VA, EL2, Inner Shareable
case MISCREG_TLBI_VAE2IS_Xt:
case MISCREG_TLBI_VAE2IS:
// AArch64 TLB Invalidate by VA, EL2, Outer Shareable
// We are currently not distinguishing Inner and Outer domains.
// We therefore implement TLBIOS instructions as TLBIIS
case MISCREG_TLBI_VAE2OS_Xt:
case MISCREG_TLBI_VAE2OS:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
@@ -507,11 +507,11 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
// AArch64 TLB Invalidate by VA, Last Level, EL2, Inner Shareable
case MISCREG_TLBI_VALE2IS_Xt:
case MISCREG_TLBI_VALE2IS:
// AArch64 TLB Invalidate by VA, Last Level, EL2, Outer Shareable
// We are currently not distinguishing Inner and Outer domains.
// We therefore implement TLBIOS instructions as TLBIIS
case MISCREG_TLBI_VALE2OS_Xt:
case MISCREG_TLBI_VALE2OS:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
@@ -536,7 +536,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
// AArch64 TLB Invalidate by VA, EL1
case MISCREG_TLBI_VAE1_Xt:
case MISCREG_TLBI_VAE1:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
auto asid = asid_16bits ? bits(value, 63, 48) :
@@ -559,7 +559,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
// AArch64 TLB Invalidate by VA, Last Level, EL1
case MISCREG_TLBI_VALE1_Xt:
case MISCREG_TLBI_VALE1:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
auto asid = asid_16bits ? bits(value, 63, 48) :
@@ -582,11 +582,11 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
// AArch64 TLB Invalidate by VA, EL1, Inner Shareable
case MISCREG_TLBI_VAE1IS_Xt:
case MISCREG_TLBI_VAE1IS:
// AArch64 TLB Invalidate by VA, EL1, Outer Shareable
// We are currently not distinguishing Inner and Outer domains.
// We therefore implement TLBIOS instructions as TLBIIS
case MISCREG_TLBI_VAE1OS_Xt:
case MISCREG_TLBI_VAE1OS:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
auto asid = asid_16bits ? bits(value, 63, 48) :
@@ -608,7 +608,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
tlbiOp.broadcast(tc);
return;
}
case MISCREG_TLBI_VALE1IS_Xt:
case MISCREG_TLBI_VALE1IS:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
auto asid = asid_16bits ? bits(value, 63, 48) :
@@ -631,7 +631,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
// AArch64 TLB Invalidate by ASID, EL1
case MISCREG_TLBI_ASIDE1_Xt:
case MISCREG_TLBI_ASIDE1:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
auto asid = asid_16bits ? bits(value, 63, 48) :
@@ -651,11 +651,11 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
// AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
case MISCREG_TLBI_ASIDE1IS_Xt:
case MISCREG_TLBI_ASIDE1IS:
// AArch64 TLB Invalidate by ASID, EL1, Outer Shareable
// We are currently not distinguishing Inner and Outer domains.
// We therefore implement TLBIOS instructions as TLBIIS
case MISCREG_TLBI_ASIDE1OS_Xt:
case MISCREG_TLBI_ASIDE1OS:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
auto asid = asid_16bits ? bits(value, 63, 48) :
@@ -675,7 +675,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
// AArch64 TLB Invalidate by VA, All ASID, EL1
case MISCREG_TLBI_VAAE1_Xt:
case MISCREG_TLBI_VAAE1:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -696,7 +696,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
// AArch64 TLB Invalidate by VA, Last Level, All ASID, EL1
case MISCREG_TLBI_VAALE1_Xt:
case MISCREG_TLBI_VAALE1:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -717,11 +717,11 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
return;
}
// AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
case MISCREG_TLBI_VAAE1IS_Xt:
case MISCREG_TLBI_VAAE1IS:
// AArch64 TLB Invalidate by VA, All ASID, EL1, Outer Shareable
// We are currently not distinguishing Inner and Outer domains.
// We therefore implement TLBIOS instructions as TLBIIS
case MISCREG_TLBI_VAAE1OS_Xt:
case MISCREG_TLBI_VAAE1OS:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -743,12 +743,12 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
}
// AArch64 TLB Invalidate by VA, All ASID,
// Last Level, EL1, Inner Shareable
case MISCREG_TLBI_VAALE1IS_Xt:
case MISCREG_TLBI_VAALE1IS:
// AArch64 TLB Invalidate by VA, All ASID,
// Last Level, EL1, Outer Shareable
// We are currently not distinguishing Inner and Outer domains.
// We therefore implement TLBIOS instructions as TLBIIS
case MISCREG_TLBI_VAALE1OS_Xt:
case MISCREG_TLBI_VAALE1OS:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -770,7 +770,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
}
// AArch64 TLB Invalidate by Intermediate Physical Address,
// Stage 2, EL1
case MISCREG_TLBI_IPAS2E1_Xt:
case MISCREG_TLBI_IPAS2E1:
{
if (EL2Enabled(tc)) {
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -790,7 +790,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
}
// AArch64 TLB Invalidate by Intermediate Physical Address,
// Stage 2, Last Level EL1
case MISCREG_TLBI_IPAS2LE1_Xt:
case MISCREG_TLBI_IPAS2LE1:
{
if (EL2Enabled(tc)) {
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -808,12 +808,12 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
}
// AArch64 TLB Invalidate by Intermediate Physical Address,
// Stage 2, EL1, Inner Shareable
case MISCREG_TLBI_IPAS2E1IS_Xt:
case MISCREG_TLBI_IPAS2E1IS:
// AArch64 TLB Invalidate by Intermediate Physical Address,
// Stage 2, EL1, Outer Shareable
// We are currently not distinguishing Inner and Outer domains.
// We therefore implement TLBIOS instructions as TLBIIS
case MISCREG_TLBI_IPAS2E1OS_Xt:
case MISCREG_TLBI_IPAS2E1OS:
{
if (EL2Enabled(tc)) {
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -833,12 +833,12 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
}
// AArch64 TLB Invalidate by Intermediate Physical Address,
// Stage 2, Last Level, EL1, Inner Shareable
case MISCREG_TLBI_IPAS2LE1IS_Xt:
case MISCREG_TLBI_IPAS2LE1IS:
// AArch64 TLB Invalidate by Intermediate Physical Address,
// Stage 2, Last Level, EL1, Outer Shareable
// We are currently not distinguishing Inner and Outer domains.
// We therefore implement TLBIOS instructions as TLBIIS
case MISCREG_TLBI_IPAS2LE1OS_Xt:
case MISCREG_TLBI_IPAS2LE1OS:
{
if (EL2Enabled(tc)) {
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -854,7 +854,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
}
return;
}
case MISCREG_TLBI_RVAE1_Xt:
case MISCREG_TLBI_RVAE1:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
auto asid = asid_16bits ? bits(value, 63, 48) :
@@ -875,8 +875,8 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
tlbiOp(tc);
return;
}
case MISCREG_TLBI_RVAE1IS_Xt:
case MISCREG_TLBI_RVAE1OS_Xt:
case MISCREG_TLBI_RVAE1IS:
case MISCREG_TLBI_RVAE1OS:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
auto asid = asid_16bits ? bits(value, 63, 48) :
@@ -897,7 +897,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
tlbiOp.broadcast(tc);
return;
}
case MISCREG_TLBI_RVAAE1_Xt:
case MISCREG_TLBI_RVAAE1:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -916,8 +916,8 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
tlbiOp(tc);
return;
}
case MISCREG_TLBI_RVAAE1IS_Xt:
case MISCREG_TLBI_RVAAE1OS_Xt:
case MISCREG_TLBI_RVAAE1IS:
case MISCREG_TLBI_RVAAE1OS:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -936,7 +936,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
tlbiOp.broadcast(tc);
return;
}
case MISCREG_TLBI_RVALE1_Xt:
case MISCREG_TLBI_RVALE1:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
auto asid = asid_16bits ? bits(value, 63, 48) :
@@ -957,8 +957,8 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
tlbiOp(tc);
return;
}
case MISCREG_TLBI_RVALE1IS_Xt:
case MISCREG_TLBI_RVALE1OS_Xt:
case MISCREG_TLBI_RVALE1IS:
case MISCREG_TLBI_RVALE1OS:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
auto asid = asid_16bits ? bits(value, 63, 48) :
@@ -979,7 +979,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
tlbiOp.broadcast(tc);
return;
}
case MISCREG_TLBI_RVAALE1_Xt:
case MISCREG_TLBI_RVAALE1:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -998,8 +998,8 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
tlbiOp(tc);
return;
}
case MISCREG_TLBI_RVAALE1IS_Xt:
case MISCREG_TLBI_RVAALE1OS_Xt:
case MISCREG_TLBI_RVAALE1IS:
case MISCREG_TLBI_RVAALE1OS:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -1018,7 +1018,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
tlbiOp.broadcast(tc);
return;
}
case MISCREG_TLBI_RIPAS2E1_Xt:
case MISCREG_TLBI_RIPAS2E1:
{
if (EL2Enabled(tc)) {
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -1032,7 +1032,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
}
return;
}
case MISCREG_TLBI_RIPAS2E1IS_Xt:
case MISCREG_TLBI_RIPAS2E1IS:
{
if (EL2Enabled(tc)) {
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -1046,7 +1046,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
}
return;
}
case MISCREG_TLBI_RIPAS2LE1_Xt:
case MISCREG_TLBI_RIPAS2LE1:
{
if (EL2Enabled(tc)) {
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -1060,7 +1060,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
}
return;
}
case MISCREG_TLBI_RIPAS2LE1IS_Xt:
case MISCREG_TLBI_RIPAS2LE1IS:
{
if (EL2Enabled(tc)) {
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
@@ -1074,7 +1074,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
}
return;
}
case MISCREG_TLBI_RVAE2_Xt:
case MISCREG_TLBI_RVAE2:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
@@ -1098,8 +1098,8 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
}
return;
}
case MISCREG_TLBI_RVAE2IS_Xt:
case MISCREG_TLBI_RVAE2OS_Xt:
case MISCREG_TLBI_RVAE2IS:
case MISCREG_TLBI_RVAE2OS:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
@@ -1123,7 +1123,7 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
}
return;
}
case MISCREG_TLBI_RVALE2_Xt:
case MISCREG_TLBI_RVALE2:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
@@ -1147,8 +1147,8 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
}
return;
}
case MISCREG_TLBI_RVALE2IS_Xt:
case MISCREG_TLBI_RVALE2OS_Xt:
case MISCREG_TLBI_RVALE2IS:
case MISCREG_TLBI_RVALE2OS:
{
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
@@ -1172,30 +1172,30 @@ TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) cons
}
return;
}
case MISCREG_TLBI_RVAE3_Xt:
case MISCREG_TLBI_RVAE3:
{
TLBIRMVAA tlbiOp(EL3, true, value, false);
if (tlbiOp.valid())
tlbiOp(tc);
return;
}
case MISCREG_TLBI_RVAE3IS_Xt:
case MISCREG_TLBI_RVAE3OS_Xt:
case MISCREG_TLBI_RVAE3IS:
case MISCREG_TLBI_RVAE3OS:
{
TLBIRMVAA tlbiOp(EL3, true, value, false);
if (tlbiOp.valid())
tlbiOp.broadcast(tc);
return;
}
case MISCREG_TLBI_RVALE3_Xt:
case MISCREG_TLBI_RVALE3:
{
TLBIRMVAA tlbiOp(EL3, true, value, true);
if (tlbiOp.valid())
tlbiOp(tc);
return;
}
case MISCREG_TLBI_RVALE3IS_Xt:
case MISCREG_TLBI_RVALE3OS_Xt:
case MISCREG_TLBI_RVALE3IS:
case MISCREG_TLBI_RVALE3OS:
{
TLBIRMVAA tlbiOp(EL3, true, value, true);
if (tlbiOp.valid())

126
src/arch/arm/isa/formats/aarch64.isa
View File

@@ -531,27 +531,27 @@ namespace Aarch64
case MISCREG_TLBI_ALLE1:
case MISCREG_TLBI_VMALLS12E1:
case MISCREG_TLBI_VMALLE1:
case MISCREG_TLBI_VAE3_Xt:
case MISCREG_TLBI_VALE3_Xt:
case MISCREG_TLBI_VAE2_Xt:
case MISCREG_TLBI_VALE2_Xt:
case MISCREG_TLBI_VAE1_Xt:
case MISCREG_TLBI_VALE1_Xt:
case MISCREG_TLBI_ASIDE1_Xt:
case MISCREG_TLBI_VAAE1_Xt:
case MISCREG_TLBI_VAALE1_Xt:
case MISCREG_TLBI_IPAS2E1_Xt:
case MISCREG_TLBI_IPAS2LE1_Xt:
case MISCREG_TLBI_RVAE1_Xt:
case MISCREG_TLBI_RVAAE1_Xt:
case MISCREG_TLBI_RVALE1_Xt:
case MISCREG_TLBI_RVAALE1_Xt:
case MISCREG_TLBI_RIPAS2E1_Xt:
case MISCREG_TLBI_RIPAS2LE1_Xt:
case MISCREG_TLBI_RVAE2_Xt:
case MISCREG_TLBI_RVALE2_Xt:
case MISCREG_TLBI_RVAE3_Xt:
case MISCREG_TLBI_RVALE3_Xt:
case MISCREG_TLBI_VAE3:
case MISCREG_TLBI_VALE3:
case MISCREG_TLBI_VAE2:
case MISCREG_TLBI_VALE2:
case MISCREG_TLBI_VAE1:
case MISCREG_TLBI_VALE1:
case MISCREG_TLBI_ASIDE1:
case MISCREG_TLBI_VAAE1:
case MISCREG_TLBI_VAALE1:
case MISCREG_TLBI_IPAS2E1:
case MISCREG_TLBI_IPAS2LE1:
case MISCREG_TLBI_RVAE1:
case MISCREG_TLBI_RVAAE1:
case MISCREG_TLBI_RVALE1:
case MISCREG_TLBI_RVAALE1:
case MISCREG_TLBI_RIPAS2E1:
case MISCREG_TLBI_RIPAS2LE1:
case MISCREG_TLBI_RVAE2:
case MISCREG_TLBI_RVALE2:
case MISCREG_TLBI_RVAE3:
case MISCREG_TLBI_RVALE3:
return new Tlbi64LocalHub(
machInst, miscReg, rt);
case MISCREG_TLBI_ALLE3IS:
@@ -564,48 +564,48 @@ namespace Aarch64
case MISCREG_TLBI_VMALLS12E1OS:
case MISCREG_TLBI_VMALLE1IS:
case MISCREG_TLBI_VMALLE1OS:
case MISCREG_TLBI_VAE3IS_Xt:
case MISCREG_TLBI_VAE3OS_Xt:
case MISCREG_TLBI_VALE3IS_Xt:
case MISCREG_TLBI_VALE3OS_Xt:
case MISCREG_TLBI_VAE2IS_Xt:
case MISCREG_TLBI_VAE2OS_Xt:
case MISCREG_TLBI_VALE2IS_Xt:
case MISCREG_TLBI_VALE2OS_Xt:
case MISCREG_TLBI_VAE1IS_Xt:
case MISCREG_TLBI_VAE1OS_Xt:
case MISCREG_TLBI_VALE1IS_Xt:
case MISCREG_TLBI_VALE1OS_Xt:
case MISCREG_TLBI_ASIDE1IS_Xt:
case MISCREG_TLBI_ASIDE1OS_Xt:
case MISCREG_TLBI_VAAE1IS_Xt:
case MISCREG_TLBI_VAAE1OS_Xt:
case MISCREG_TLBI_VAALE1IS_Xt:
case MISCREG_TLBI_VAALE1OS_Xt:
case MISCREG_TLBI_IPAS2E1IS_Xt:
case MISCREG_TLBI_IPAS2E1OS_Xt:
case MISCREG_TLBI_IPAS2LE1IS_Xt:
case MISCREG_TLBI_IPAS2LE1OS_Xt:
case MISCREG_TLBI_RVAE1IS_Xt:
case MISCREG_TLBI_RVAE1OS_Xt:
case MISCREG_TLBI_RVAAE1IS_Xt:
case MISCREG_TLBI_RVAAE1OS_Xt:
case MISCREG_TLBI_RVALE1IS_Xt:
case MISCREG_TLBI_RVALE1OS_Xt:
case MISCREG_TLBI_RVAALE1IS_Xt:
case MISCREG_TLBI_RVAALE1OS_Xt:
case MISCREG_TLBI_RIPAS2E1IS_Xt:
case MISCREG_TLBI_RIPAS2E1OS_Xt:
case MISCREG_TLBI_RIPAS2LE1IS_Xt:
case MISCREG_TLBI_RIPAS2LE1OS_Xt:
case MISCREG_TLBI_RVAE2IS_Xt:
case MISCREG_TLBI_RVAE2OS_Xt:
case MISCREG_TLBI_RVALE2IS_Xt:
case MISCREG_TLBI_RVALE2OS_Xt:
case MISCREG_TLBI_RVAE3IS_Xt:
case MISCREG_TLBI_RVAE3OS_Xt:
case MISCREG_TLBI_RVALE3IS_Xt:
case MISCREG_TLBI_RVALE3OS_Xt:
case MISCREG_TLBI_VAE3IS:
case MISCREG_TLBI_VAE3OS:
case MISCREG_TLBI_VALE3IS:
case MISCREG_TLBI_VALE3OS:
case MISCREG_TLBI_VAE2IS:
case MISCREG_TLBI_VAE2OS:
case MISCREG_TLBI_VALE2IS:
case MISCREG_TLBI_VALE2OS:
case MISCREG_TLBI_VAE1IS:
case MISCREG_TLBI_VAE1OS:
case MISCREG_TLBI_VALE1IS:
case MISCREG_TLBI_VALE1OS:
case MISCREG_TLBI_ASIDE1IS:
case MISCREG_TLBI_ASIDE1OS:
case MISCREG_TLBI_VAAE1IS:
case MISCREG_TLBI_VAAE1OS:
case MISCREG_TLBI_VAALE1IS:
case MISCREG_TLBI_VAALE1OS:
case MISCREG_TLBI_IPAS2E1IS:
case MISCREG_TLBI_IPAS2E1OS:
case MISCREG_TLBI_IPAS2LE1IS:
case MISCREG_TLBI_IPAS2LE1OS:
case MISCREG_TLBI_RVAE1IS:
case MISCREG_TLBI_RVAE1OS:
case MISCREG_TLBI_RVAAE1IS:
case MISCREG_TLBI_RVAAE1OS:
case MISCREG_TLBI_RVALE1IS:
case MISCREG_TLBI_RVALE1OS:
case MISCREG_TLBI_RVAALE1IS:
case MISCREG_TLBI_RVAALE1OS:
case MISCREG_TLBI_RIPAS2E1IS:
case MISCREG_TLBI_RIPAS2E1OS:
case MISCREG_TLBI_RIPAS2LE1IS:
case MISCREG_TLBI_RIPAS2LE1OS:
case MISCREG_TLBI_RVAE2IS:
case MISCREG_TLBI_RVAE2OS:
case MISCREG_TLBI_RVALE2IS:
case MISCREG_TLBI_RVALE2OS:
case MISCREG_TLBI_RVAE3IS:
case MISCREG_TLBI_RVAE3OS:
case MISCREG_TLBI_RVALE3IS:
case MISCREG_TLBI_RVALE3OS:
return new Tlbi64ShareableHub(
machInst, miscReg, rt, dec.dvmEnabled);
default:

252
src/arch/arm/regs/misc.cc
View File

@@ -754,35 +754,35 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
{ MiscRegNum64(1, 0, 7, 10, 2), MISCREG_DC_CSW_Xt },
{ MiscRegNum64(1, 0, 7, 14, 2), MISCREG_DC_CISW_Xt },
{ MiscRegNum64(1, 0, 8, 1, 0), MISCREG_TLBI_VMALLE1OS },
{ MiscRegNum64(1, 0, 8, 1, 1), MISCREG_TLBI_VAE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 1, 2), MISCREG_TLBI_ASIDE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 1, 3), MISCREG_TLBI_VAAE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 1, 5), MISCREG_TLBI_VALE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 1, 7), MISCREG_TLBI_VAALE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 2, 1), MISCREG_TLBI_RVAE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 2, 3), MISCREG_TLBI_RVAAE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 2, 5), MISCREG_TLBI_RVALE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 2, 7), MISCREG_TLBI_RVAALE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 1, 1), MISCREG_TLBI_VAE1OS },
{ MiscRegNum64(1, 0, 8, 1, 2), MISCREG_TLBI_ASIDE1OS },
{ MiscRegNum64(1, 0, 8, 1, 3), MISCREG_TLBI_VAAE1OS },
{ MiscRegNum64(1, 0, 8, 1, 5), MISCREG_TLBI_VALE1OS },
{ MiscRegNum64(1, 0, 8, 1, 7), MISCREG_TLBI_VAALE1OS },
{ MiscRegNum64(1, 0, 8, 2, 1), MISCREG_TLBI_RVAE1IS },
{ MiscRegNum64(1, 0, 8, 2, 3), MISCREG_TLBI_RVAAE1IS },
{ MiscRegNum64(1, 0, 8, 2, 5), MISCREG_TLBI_RVALE1IS },
{ MiscRegNum64(1, 0, 8, 2, 7), MISCREG_TLBI_RVAALE1IS },
{ MiscRegNum64(1, 0, 8, 3, 0), MISCREG_TLBI_VMALLE1IS },
{ MiscRegNum64(1, 0, 8, 3, 1), MISCREG_TLBI_VAE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 3, 2), MISCREG_TLBI_ASIDE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 3, 3), MISCREG_TLBI_VAAE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 3, 5), MISCREG_TLBI_VALE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 3, 7), MISCREG_TLBI_VAALE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 5, 1), MISCREG_TLBI_RVAE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 5, 3), MISCREG_TLBI_RVAAE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 5, 5), MISCREG_TLBI_RVALE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 5, 7), MISCREG_TLBI_RVAALE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 6, 1), MISCREG_TLBI_RVAE1_Xt },
{ MiscRegNum64(1, 0, 8, 6, 3), MISCREG_TLBI_RVAAE1_Xt },
{ MiscRegNum64(1, 0, 8, 6, 5), MISCREG_TLBI_RVALE1_Xt },
{ MiscRegNum64(1, 0, 8, 6, 7), MISCREG_TLBI_RVAALE1_Xt },
{ MiscRegNum64(1, 0, 8, 3, 1), MISCREG_TLBI_VAE1IS },
{ MiscRegNum64(1, 0, 8, 3, 2), MISCREG_TLBI_ASIDE1IS },
{ MiscRegNum64(1, 0, 8, 3, 3), MISCREG_TLBI_VAAE1IS },
{ MiscRegNum64(1, 0, 8, 3, 5), MISCREG_TLBI_VALE1IS },
{ MiscRegNum64(1, 0, 8, 3, 7), MISCREG_TLBI_VAALE1IS },
{ MiscRegNum64(1, 0, 8, 5, 1), MISCREG_TLBI_RVAE1OS },
{ MiscRegNum64(1, 0, 8, 5, 3), MISCREG_TLBI_RVAAE1OS },
{ MiscRegNum64(1, 0, 8, 5, 5), MISCREG_TLBI_RVALE1OS },
{ MiscRegNum64(1, 0, 8, 5, 7), MISCREG_TLBI_RVAALE1OS },
{ MiscRegNum64(1, 0, 8, 6, 1), MISCREG_TLBI_RVAE1 },
{ MiscRegNum64(1, 0, 8, 6, 3), MISCREG_TLBI_RVAAE1 },
{ MiscRegNum64(1, 0, 8, 6, 5), MISCREG_TLBI_RVALE1 },
{ MiscRegNum64(1, 0, 8, 6, 7), MISCREG_TLBI_RVAALE1 },
{ MiscRegNum64(1, 0, 8, 7, 0), MISCREG_TLBI_VMALLE1 },
{ MiscRegNum64(1, 0, 8, 7, 1), MISCREG_TLBI_VAE1_Xt },
{ MiscRegNum64(1, 0, 8, 7, 2), MISCREG_TLBI_ASIDE1_Xt },
{ MiscRegNum64(1, 0, 8, 7, 3), MISCREG_TLBI_VAAE1_Xt },
{ MiscRegNum64(1, 0, 8, 7, 5), MISCREG_TLBI_VALE1_Xt },
{ MiscRegNum64(1, 0, 8, 7, 7), MISCREG_TLBI_VAALE1_Xt },
{ MiscRegNum64(1, 0, 8, 7, 1), MISCREG_TLBI_VAE1 },
{ MiscRegNum64(1, 0, 8, 7, 2), MISCREG_TLBI_ASIDE1 },
{ MiscRegNum64(1, 0, 8, 7, 3), MISCREG_TLBI_VAAE1 },
{ MiscRegNum64(1, 0, 8, 7, 5), MISCREG_TLBI_VALE1 },
{ MiscRegNum64(1, 0, 8, 7, 7), MISCREG_TLBI_VAALE1 },
{ MiscRegNum64(1, 3, 7, 4, 1), MISCREG_DC_ZVA_Xt },
{ MiscRegNum64(1, 3, 7, 5, 1), MISCREG_IC_IVAU_Xt },
{ MiscRegNum64(1, 3, 7, 10, 1), MISCREG_DC_CVAC_Xt },
@@ -794,56 +794,56 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
{ MiscRegNum64(1, 4, 7, 8, 5), MISCREG_AT_S12E1W_Xt },
{ MiscRegNum64(1, 4, 7, 8, 6), MISCREG_AT_S12E0R_Xt },
{ MiscRegNum64(1, 4, 7, 8, 7), MISCREG_AT_S12E0W_Xt },
{ MiscRegNum64(1, 4, 8, 0, 1), MISCREG_TLBI_IPAS2E1IS_Xt },
{ MiscRegNum64(1, 4, 8, 0, 2), MISCREG_TLBI_RIPAS2E1IS_Xt },
{ MiscRegNum64(1, 4, 8, 0, 5), MISCREG_TLBI_IPAS2LE1IS_Xt },
{ MiscRegNum64(1, 4, 8, 0, 1), MISCREG_TLBI_IPAS2E1IS },
{ MiscRegNum64(1, 4, 8, 0, 2), MISCREG_TLBI_RIPAS2E1IS },
{ MiscRegNum64(1, 4, 8, 0, 5), MISCREG_TLBI_IPAS2LE1IS },
{ MiscRegNum64(1, 4, 8, 1, 0), MISCREG_TLBI_ALLE2OS },
{ MiscRegNum64(1, 4, 8, 1, 1), MISCREG_TLBI_VAE2OS_Xt },
{ MiscRegNum64(1, 4, 8, 1, 1), MISCREG_TLBI_VAE2OS },
{ MiscRegNum64(1, 4, 8, 1, 4), MISCREG_TLBI_ALLE1OS },
{ MiscRegNum64(1, 4, 8, 1, 5), MISCREG_TLBI_VALE2OS_Xt },
{ MiscRegNum64(1, 4, 8, 1, 5), MISCREG_TLBI_VALE2OS },
{ MiscRegNum64(1, 4, 8, 1, 6), MISCREG_TLBI_VMALLS12E1OS },
{ MiscRegNum64(1, 4, 8, 0, 6), MISCREG_TLBI_RIPAS2LE1IS_Xt },
{ MiscRegNum64(1, 4, 8, 2, 1), MISCREG_TLBI_RVAE2IS_Xt },
{ MiscRegNum64(1, 4, 8, 2, 5), MISCREG_TLBI_RVALE2IS_Xt },
{ MiscRegNum64(1, 4, 8, 0, 6), MISCREG_TLBI_RIPAS2LE1IS },
{ MiscRegNum64(1, 4, 8, 2, 1), MISCREG_TLBI_RVAE2IS },
{ MiscRegNum64(1, 4, 8, 2, 5), MISCREG_TLBI_RVALE2IS },
{ MiscRegNum64(1, 4, 8, 3, 0), MISCREG_TLBI_ALLE2IS },
{ MiscRegNum64(1, 4, 8, 3, 1), MISCREG_TLBI_VAE2IS_Xt },
{ MiscRegNum64(1, 4, 8, 3, 1), MISCREG_TLBI_VAE2IS },
{ MiscRegNum64(1, 4, 8, 3, 4), MISCREG_TLBI_ALLE1IS },
{ MiscRegNum64(1, 4, 8, 3, 5), MISCREG_TLBI_VALE2IS_Xt },
{ MiscRegNum64(1, 4, 8, 3, 5), MISCREG_TLBI_VALE2IS },
{ MiscRegNum64(1, 4, 8, 3, 6), MISCREG_TLBI_VMALLS12E1IS },
{ MiscRegNum64(1, 4, 8, 4, 0), MISCREG_TLBI_IPAS2E1OS_Xt },
{ MiscRegNum64(1, 4, 8, 4, 1), MISCREG_TLBI_IPAS2E1_Xt },
{ MiscRegNum64(1, 4, 8, 4, 2), MISCREG_TLBI_RIPAS2E1_Xt },
{ MiscRegNum64(1, 4, 8, 4, 3), MISCREG_TLBI_RIPAS2E1OS_Xt },
{ MiscRegNum64(1, 4, 8, 4, 4), MISCREG_TLBI_IPAS2LE1OS_Xt },
{ MiscRegNum64(1, 4, 8, 4, 5), MISCREG_TLBI_IPAS2LE1_Xt },
{ MiscRegNum64(1, 4, 8, 4, 6), MISCREG_TLBI_RIPAS2LE1_Xt },
{ MiscRegNum64(1, 4, 8, 4, 7), MISCREG_TLBI_RIPAS2LE1OS_Xt },
{ MiscRegNum64(1, 4, 8, 5, 1), MISCREG_TLBI_RVAE2OS_Xt },
{ MiscRegNum64(1, 4, 8, 5, 5), MISCREG_TLBI_RVALE2OS_Xt },
{ MiscRegNum64(1, 4, 8, 6, 1), MISCREG_TLBI_RVAE2_Xt },
{ MiscRegNum64(1, 4, 8, 6, 5), MISCREG_TLBI_RVALE2_Xt },
{ MiscRegNum64(1, 4, 8, 4, 0), MISCREG_TLBI_IPAS2E1OS },
{ MiscRegNum64(1, 4, 8, 4, 1), MISCREG_TLBI_IPAS2E1 },
{ MiscRegNum64(1, 4, 8, 4, 2), MISCREG_TLBI_RIPAS2E1 },
{ MiscRegNum64(1, 4, 8, 4, 3), MISCREG_TLBI_RIPAS2E1OS },
{ MiscRegNum64(1, 4, 8, 4, 4), MISCREG_TLBI_IPAS2LE1OS },
{ MiscRegNum64(1, 4, 8, 4, 5), MISCREG_TLBI_IPAS2LE1 },
{ MiscRegNum64(1, 4, 8, 4, 6), MISCREG_TLBI_RIPAS2LE1 },
{ MiscRegNum64(1, 4, 8, 4, 7), MISCREG_TLBI_RIPAS2LE1OS },
{ MiscRegNum64(1, 4, 8, 5, 1), MISCREG_TLBI_RVAE2OS },
{ MiscRegNum64(1, 4, 8, 5, 5), MISCREG_TLBI_RVALE2OS },
{ MiscRegNum64(1, 4, 8, 6, 1), MISCREG_TLBI_RVAE2 },
{ MiscRegNum64(1, 4, 8, 6, 5), MISCREG_TLBI_RVALE2 },
{ MiscRegNum64(1, 4, 8, 7, 0), MISCREG_TLBI_ALLE2 },
{ MiscRegNum64(1, 4, 8, 7, 1), MISCREG_TLBI_VAE2_Xt },
{ MiscRegNum64(1, 4, 8, 7, 1), MISCREG_TLBI_VAE2 },
{ MiscRegNum64(1, 4, 8, 7, 4), MISCREG_TLBI_ALLE1 },
{ MiscRegNum64(1, 4, 8, 7, 5), MISCREG_TLBI_VALE2_Xt },
{ MiscRegNum64(1, 4, 8, 7, 5), MISCREG_TLBI_VALE2 },
{ MiscRegNum64(1, 4, 8, 7, 6), MISCREG_TLBI_VMALLS12E1 },
{ MiscRegNum64(1, 6, 7, 8, 0), MISCREG_AT_S1E3R_Xt },
{ MiscRegNum64(1, 6, 7, 8, 1), MISCREG_AT_S1E3W_Xt },
{ MiscRegNum64(1, 6, 8, 1, 0), MISCREG_TLBI_ALLE3OS },
{ MiscRegNum64(1, 6, 8, 1, 1), MISCREG_TLBI_VAE3OS_Xt },
{ MiscRegNum64(1, 6, 8, 1, 5), MISCREG_TLBI_VALE3OS_Xt },
{ MiscRegNum64(1, 6, 8, 2, 1), MISCREG_TLBI_RVAE3IS_Xt },
{ MiscRegNum64(1, 6, 8, 2, 5), MISCREG_TLBI_RVALE3IS_Xt },
{ MiscRegNum64(1, 6, 8, 1, 1), MISCREG_TLBI_VAE3OS },
{ MiscRegNum64(1, 6, 8, 1, 5), MISCREG_TLBI_VALE3OS },
{ MiscRegNum64(1, 6, 8, 2, 1), MISCREG_TLBI_RVAE3IS },
{ MiscRegNum64(1, 6, 8, 2, 5), MISCREG_TLBI_RVALE3IS },
{ MiscRegNum64(1, 6, 8, 3, 0), MISCREG_TLBI_ALLE3IS },
{ MiscRegNum64(1, 6, 8, 3, 1), MISCREG_TLBI_VAE3IS_Xt },
{ MiscRegNum64(1, 6, 8, 3, 5), MISCREG_TLBI_VALE3IS_Xt },
{ MiscRegNum64(1, 6, 8, 5, 1), MISCREG_TLBI_RVAE3OS_Xt },
{ MiscRegNum64(1, 6, 8, 5, 5), MISCREG_TLBI_RVALE3OS_Xt },
{ MiscRegNum64(1, 6, 8, 6, 1), MISCREG_TLBI_RVAE3_Xt },
{ MiscRegNum64(1, 6, 8, 6, 5), MISCREG_TLBI_RVALE3_Xt },
{ MiscRegNum64(1, 6, 8, 3, 1), MISCREG_TLBI_VAE3IS },
{ MiscRegNum64(1, 6, 8, 3, 5), MISCREG_TLBI_VALE3IS },
{ MiscRegNum64(1, 6, 8, 5, 1), MISCREG_TLBI_RVAE3OS },
{ MiscRegNum64(1, 6, 8, 5, 5), MISCREG_TLBI_RVALE3OS },
{ MiscRegNum64(1, 6, 8, 6, 1), MISCREG_TLBI_RVAE3 },
{ MiscRegNum64(1, 6, 8, 6, 5), MISCREG_TLBI_RVALE3 },
{ MiscRegNum64(1, 6, 8, 7, 0), MISCREG_TLBI_ALLE3 },
{ MiscRegNum64(1, 6, 8, 7, 1), MISCREG_TLBI_VAE3_Xt },
{ MiscRegNum64(1, 6, 8, 7, 5), MISCREG_TLBI_VALE3_Xt },
{ MiscRegNum64(1, 6, 8, 7, 1), MISCREG_TLBI_VAE3 },
{ MiscRegNum64(1, 6, 8, 7, 5), MISCREG_TLBI_VALE3 },
{ MiscRegNum64(2, 0, 0, 0, 2), MISCREG_OSDTRRX_EL1 },
{ MiscRegNum64(2, 0, 0, 0, 4), MISCREG_DBGBVR0_EL1 },
{ MiscRegNum64(2, 0, 0, 0, 5), MISCREG_DBGBCR0_EL1 },
@@ -4998,189 +4998,189 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_TLBI_VMALLE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivmalle1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAE1OS_Xt)
InitReg(MISCREG_TLBI_VAE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivae1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_ASIDE1OS_Xt)
InitReg(MISCREG_TLBI_ASIDE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbiaside1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAAE1OS_Xt)
InitReg(MISCREG_TLBI_VAAE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivaae1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VALE1OS_Xt)
InitReg(MISCREG_TLBI_VALE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivale1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAALE1OS_Xt)
InitReg(MISCREG_TLBI_VAALE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivaale1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VMALLE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivmalle1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAE1IS_Xt)
InitReg(MISCREG_TLBI_VAE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivae1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
InitReg(MISCREG_TLBI_ASIDE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbiaside1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAAE1IS_Xt)
InitReg(MISCREG_TLBI_VAAE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivaae1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VALE1IS_Xt)
InitReg(MISCREG_TLBI_VALE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivale1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAALE1IS_Xt)
InitReg(MISCREG_TLBI_VAALE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivaale1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VMALLE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivmalle1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAE1_Xt)
InitReg(MISCREG_TLBI_VAE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivae1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_ASIDE1_Xt)
InitReg(MISCREG_TLBI_ASIDE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbiaside1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAAE1_Xt)
InitReg(MISCREG_TLBI_VAAE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivaae1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VALE1_Xt)
InitReg(MISCREG_TLBI_VALE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivale1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAALE1_Xt)
InitReg(MISCREG_TLBI_VAALE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivaale1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_IPAS2E1OS_Xt)
InitReg(MISCREG_TLBI_IPAS2E1OS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_IPAS2LE1OS_Xt)
InitReg(MISCREG_TLBI_IPAS2LE1OS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_ALLE2OS)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_VAE2OS_Xt)
InitReg(MISCREG_TLBI_VAE2OS)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_ALLE1OS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VALE2OS_Xt)
InitReg(MISCREG_TLBI_VALE2OS)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_VMALLS12E1OS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
InitReg(MISCREG_TLBI_IPAS2E1IS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
InitReg(MISCREG_TLBI_IPAS2LE1IS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_ALLE2IS)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_VAE2IS_Xt)
InitReg(MISCREG_TLBI_VAE2IS)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_ALLE1IS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VALE2IS_Xt)
InitReg(MISCREG_TLBI_VALE2IS)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_VMALLS12E1IS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_IPAS2E1_Xt)
InitReg(MISCREG_TLBI_IPAS2E1)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
InitReg(MISCREG_TLBI_IPAS2LE1)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_ALLE2)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_VAE2_Xt)
InitReg(MISCREG_TLBI_VAE2)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_ALLE1)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VALE2_Xt)
InitReg(MISCREG_TLBI_VALE2)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_VMALLS12E1)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_ALLE3OS)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VAE3OS_Xt)
InitReg(MISCREG_TLBI_VAE3OS)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VALE3OS_Xt)
InitReg(MISCREG_TLBI_VALE3OS)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_ALLE3IS)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VAE3IS_Xt)
InitReg(MISCREG_TLBI_VAE3IS)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VALE3IS_Xt)
InitReg(MISCREG_TLBI_VALE3IS)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_ALLE3)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VAE3_Xt)
InitReg(MISCREG_TLBI_VAE3)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VALE3_Xt)
InitReg(MISCREG_TLBI_VALE3)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_RVAE1_Xt)
InitReg(MISCREG_TLBI_RVAE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbirvae1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVAAE1_Xt)
InitReg(MISCREG_TLBI_RVAAE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbirvaae1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVALE1_Xt)
InitReg(MISCREG_TLBI_RVALE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbirvale1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVAALE1_Xt)
InitReg(MISCREG_TLBI_RVAALE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbirvaale1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RIPAS2E1_Xt)
InitReg(MISCREG_TLBI_RIPAS2E1)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RIPAS2LE1_Xt)
InitReg(MISCREG_TLBI_RIPAS2LE1)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVAE2_Xt)
InitReg(MISCREG_TLBI_RVAE2)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVALE2_Xt)
InitReg(MISCREG_TLBI_RVALE2)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVAE3_Xt)
InitReg(MISCREG_TLBI_RVAE3)
.monWrite();
InitReg(MISCREG_TLBI_RVALE3_Xt)
InitReg(MISCREG_TLBI_RVALE3)
.monWrite();
InitReg(MISCREG_TLBI_RVAE1IS_Xt)
InitReg(MISCREG_TLBI_RVAE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbirvae1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVAAE1IS_Xt)
InitReg(MISCREG_TLBI_RVAAE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbirvaae1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVALE1IS_Xt)
InitReg(MISCREG_TLBI_RVALE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbirvale1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVAALE1IS_Xt)
InitReg(MISCREG_TLBI_RVAALE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbirvaale1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RIPAS2E1IS_Xt)
InitReg(MISCREG_TLBI_RIPAS2E1IS)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RIPAS2LE1IS_Xt)
InitReg(MISCREG_TLBI_RIPAS2LE1IS)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVAE2IS_Xt)
InitReg(MISCREG_TLBI_RVAE2IS)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVALE2IS_Xt)
InitReg(MISCREG_TLBI_RVALE2IS)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVAE3IS_Xt)
InitReg(MISCREG_TLBI_RVAE3IS)
.monWrite();
InitReg(MISCREG_TLBI_RVALE3IS_Xt)
InitReg(MISCREG_TLBI_RVALE3IS)
.monWrite();
InitReg(MISCREG_TLBI_RVAE1OS_Xt)
InitReg(MISCREG_TLBI_RVAE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbirvae1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVAAE1OS_Xt)
InitReg(MISCREG_TLBI_RVAAE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbirvaae1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVALE1OS_Xt)
InitReg(MISCREG_TLBI_RVALE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbirvale1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVAALE1OS_Xt)
InitReg(MISCREG_TLBI_RVAALE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbirvaale1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RIPAS2E1OS_Xt)
InitReg(MISCREG_TLBI_RIPAS2E1OS)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RIPAS2LE1OS_Xt)
InitReg(MISCREG_TLBI_RIPAS2LE1OS)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVAE2OS_Xt)
InitReg(MISCREG_TLBI_RVAE2OS)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVALE2OS_Xt)
InitReg(MISCREG_TLBI_RVALE2OS)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVAE3OS_Xt)
InitReg(MISCREG_TLBI_RVAE3OS)
.monWrite();
InitReg(MISCREG_TLBI_RVALE3OS_Xt)
InitReg(MISCREG_TLBI_RVALE3OS)
.monWrite();
InitReg(MISCREG_PMINTENSET_EL1)
.allPrivileges().exceptUserMode()

252
src/arch/arm/regs/misc.hh
View File

@@ -691,82 +691,82 @@ namespace ArmISA
MISCREG_AT_S1E3W_Xt,
MISCREG_TLBI_VMALLE1IS,
MISCREG_TLBI_VMALLE1OS,
MISCREG_TLBI_VAE1IS_Xt,
MISCREG_TLBI_VAE1OS_Xt,
MISCREG_TLBI_ASIDE1IS_Xt,
MISCREG_TLBI_ASIDE1OS_Xt,
MISCREG_TLBI_VAAE1IS_Xt,
MISCREG_TLBI_VAAE1OS_Xt,
MISCREG_TLBI_VALE1IS_Xt,
MISCREG_TLBI_VALE1OS_Xt,
MISCREG_TLBI_VAALE1IS_Xt,
MISCREG_TLBI_VAALE1OS_Xt,
MISCREG_TLBI_VAE1IS,
MISCREG_TLBI_VAE1OS,
MISCREG_TLBI_ASIDE1IS,
MISCREG_TLBI_ASIDE1OS,
MISCREG_TLBI_VAAE1IS,
MISCREG_TLBI_VAAE1OS,
MISCREG_TLBI_VALE1IS,
MISCREG_TLBI_VALE1OS,
MISCREG_TLBI_VAALE1IS,
MISCREG_TLBI_VAALE1OS,
MISCREG_TLBI_VMALLE1,
MISCREG_TLBI_VAE1_Xt,
MISCREG_TLBI_ASIDE1_Xt,
MISCREG_TLBI_VAAE1_Xt,
MISCREG_TLBI_VALE1_Xt,
MISCREG_TLBI_VAALE1_Xt,
MISCREG_TLBI_IPAS2E1IS_Xt,
MISCREG_TLBI_IPAS2E1OS_Xt,
MISCREG_TLBI_IPAS2LE1IS_Xt,
MISCREG_TLBI_IPAS2LE1OS_Xt,
MISCREG_TLBI_VAE1,
MISCREG_TLBI_ASIDE1,
MISCREG_TLBI_VAAE1,
MISCREG_TLBI_VALE1,
MISCREG_TLBI_VAALE1,
MISCREG_TLBI_IPAS2E1IS,
MISCREG_TLBI_IPAS2E1OS,
MISCREG_TLBI_IPAS2LE1IS,
MISCREG_TLBI_IPAS2LE1OS,
MISCREG_TLBI_ALLE2IS,
MISCREG_TLBI_ALLE2OS,
MISCREG_TLBI_VAE2IS_Xt,
MISCREG_TLBI_VAE2OS_Xt,
MISCREG_TLBI_VAE2IS,
MISCREG_TLBI_VAE2OS,
MISCREG_TLBI_ALLE1IS,
MISCREG_TLBI_ALLE1OS,
MISCREG_TLBI_VALE2IS_Xt,
MISCREG_TLBI_VALE2OS_Xt,
MISCREG_TLBI_VALE2IS,
MISCREG_TLBI_VALE2OS,
MISCREG_TLBI_VMALLS12E1IS,
MISCREG_TLBI_VMALLS12E1OS,
MISCREG_TLBI_IPAS2E1_Xt,
MISCREG_TLBI_IPAS2LE1_Xt,
MISCREG_TLBI_IPAS2E1,
MISCREG_TLBI_IPAS2LE1,
MISCREG_TLBI_ALLE2,
MISCREG_TLBI_VAE2_Xt,
MISCREG_TLBI_VAE2,
MISCREG_TLBI_ALLE1,
MISCREG_TLBI_VALE2_Xt,
MISCREG_TLBI_VALE2,
MISCREG_TLBI_VMALLS12E1,
MISCREG_TLBI_ALLE3IS,
MISCREG_TLBI_ALLE3OS,
MISCREG_TLBI_VAE3IS_Xt,
MISCREG_TLBI_VAE3OS_Xt,
MISCREG_TLBI_VALE3IS_Xt,
MISCREG_TLBI_VALE3OS_Xt,
MISCREG_TLBI_VAE3IS,
MISCREG_TLBI_VAE3OS,
MISCREG_TLBI_VALE3IS,
MISCREG_TLBI_VALE3OS,
MISCREG_TLBI_ALLE3,
MISCREG_TLBI_VAE3_Xt,
MISCREG_TLBI_VALE3_Xt,
MISCREG_TLBI_RVAE1_Xt,
MISCREG_TLBI_RVAAE1_Xt,
MISCREG_TLBI_RVALE1_Xt,
MISCREG_TLBI_RVAALE1_Xt,
MISCREG_TLBI_RIPAS2E1_Xt,
MISCREG_TLBI_RIPAS2LE1_Xt,
MISCREG_TLBI_RVAE2_Xt,
MISCREG_TLBI_RVALE2_Xt,
MISCREG_TLBI_RVAE3_Xt,
MISCREG_TLBI_RVALE3_Xt,
MISCREG_TLBI_RVAE1IS_Xt,
MISCREG_TLBI_RVAAE1IS_Xt,
MISCREG_TLBI_RVALE1IS_Xt,
MISCREG_TLBI_RVAALE1IS_Xt,
MISCREG_TLBI_RIPAS2E1IS_Xt,
MISCREG_TLBI_RIPAS2LE1IS_Xt,
MISCREG_TLBI_RVAE2IS_Xt,
MISCREG_TLBI_RVALE2IS_Xt,
MISCREG_TLBI_RVAE3IS_Xt,
MISCREG_TLBI_RVALE3IS_Xt,
MISCREG_TLBI_RVAE1OS_Xt,
MISCREG_TLBI_RVAAE1OS_Xt,
MISCREG_TLBI_RVALE1OS_Xt,
MISCREG_TLBI_RVAALE1OS_Xt,
MISCREG_TLBI_RIPAS2E1OS_Xt,
MISCREG_TLBI_RIPAS2LE1OS_Xt,
MISCREG_TLBI_RVAE2OS_Xt,
MISCREG_TLBI_RVALE2OS_Xt,
MISCREG_TLBI_RVAE3OS_Xt,
MISCREG_TLBI_RVALE3OS_Xt,
MISCREG_TLBI_VAE3,
MISCREG_TLBI_VALE3,
MISCREG_TLBI_RVAE1,
MISCREG_TLBI_RVAAE1,
MISCREG_TLBI_RVALE1,
MISCREG_TLBI_RVAALE1,
MISCREG_TLBI_RIPAS2E1,
MISCREG_TLBI_RIPAS2LE1,
MISCREG_TLBI_RVAE2,
MISCREG_TLBI_RVALE2,
MISCREG_TLBI_RVAE3,
MISCREG_TLBI_RVALE3,
MISCREG_TLBI_RVAE1IS,
MISCREG_TLBI_RVAAE1IS,
MISCREG_TLBI_RVALE1IS,
MISCREG_TLBI_RVAALE1IS,
MISCREG_TLBI_RIPAS2E1IS,
MISCREG_TLBI_RIPAS2LE1IS,
MISCREG_TLBI_RVAE2IS,
MISCREG_TLBI_RVALE2IS,
MISCREG_TLBI_RVAE3IS,
MISCREG_TLBI_RVALE3IS,
MISCREG_TLBI_RVAE1OS,
MISCREG_TLBI_RVAAE1OS,
MISCREG_TLBI_RVALE1OS,
MISCREG_TLBI_RVAALE1OS,
MISCREG_TLBI_RIPAS2E1OS,
MISCREG_TLBI_RIPAS2LE1OS,
MISCREG_TLBI_RVAE2OS,
MISCREG_TLBI_RVALE2OS,
MISCREG_TLBI_RVAE3OS,
MISCREG_TLBI_RVALE3OS,
MISCREG_PMINTENSET_EL1,
MISCREG_PMINTENCLR_EL1,
MISCREG_PMCR_EL0,
@@ -2418,82 +2418,82 @@ namespace ArmISA
"at_s1e3w_xt",
"tlbi_vmalle1is",
"tlbi_vmalle1os",
"tlbi_vae1is_xt",
"tlbi_vae1os_xt",
"tlbi_aside1is_xt",
"tlbi_aside1os_xt",
"tlbi_vaae1is_xt",
"tlbi_vaae1os_xt",
"tlbi_vale1is_xt",
"tlbi_vale1os_xt",
"tlbi_vaale1is_xt",
"tlbi_vaale1os_xt",
"tlbi_vae1is",
"tlbi_vae1os",
"lbi_aside1is_xt",
"tlbi_aside1os",
"tlbi_vaae1is",
"tlbi_vaae1os",
"tlbi_vale1is",
"tlbi_vale1os",
"tlbi_vaale1is",
"tlbi_vaale1os",
"tlbi_vmalle1",
"tlbi_vae1_xt",
"tlbi_aside1_xt",
"tlbi_vaae1_xt",
"tlbi_vale1_xt",
"tlbi_vaale1_xt",
"tlbi_ipas2e1is_xt",
"tlbi_ipas2e1os_xt",
"tlbi_ipas2le1is_xt",
"tlbi_ipas2le1os_xt",
"tlbi_vae1",
"tlbi_aside1",
"tlbi_vaae1",
"tlbi_vale1",
"tlbi_vaale1",
"tlbi_ipas2e1is",
"tlbi_ipas2e1os",
"tlbi_ipas2le1is",
"tlbi_ipas2le1os",
"tlbi_alle2is",
"tlbi_alle2os",
"tlbi_vae2is_xt",
"tlbi_vae2os_xt",
"tlbi_vae2is",
"tlbi_vae2os",
"tlbi_alle1is",
"tlbi_alle1os",
"tlbi_vale2is_xt",
"tlbi_vale2os_xt",
"tlbi_vale2is",
"tlbi_vale2os",
"tlbi_vmalls12e1is",
"tlbi_vmalls12e1os",
"tlbi_ipas2e1_xt",
"tlbi_ipas2le1_xt",
"tlbi_ipas2e1",
"tlbi_ipas2le1",
"tlbi_alle2",
"tlbi_vae2_xt",
"tlbi_vae2",
"tlbi_alle1",
"tlbi_vale2_xt",
"tlbi_vale2",
"tlbi_vmalls12e1",
"tlbi_alle3is",
"tlbi_alle3os",
"tlbi_vae3is_xt",
"tlbi_vae3os_xt",
"tlbi_vale3is_xt",
"tlbi_vale3os_xt",
"tlbi_vae3is",
"tlbi_vae3os",
"tlbi_vale3is",
"tlbi_vale3os",
"tlbi_alle3",
"tlbi_vae3_xt",
"tlbi_vale3_xt",
"tlbi_rvae1_xt",
"tlbi_rvaae1_xt",
"tlbi_rvale1_xt",
"tlbi_rvaale1_xt",
"tlbi_ripas2e1_xt",
"tlbi_ripas2le1_xt",
"tlbi_rvae2_xt",
"tlbi_rvale2_xt",
"tlbi_rvae3_xt",
"tlbi_rvale3_xt",
"tlbi_rvae1is_xt",
"tlbi_rvaae1is_xt",
"tlbi_rvale1is_xt",
"tlbi_rvaale1is_xt",
"tlbi_ripas2e1is_xt",
"tlbi_ripas2le1is_xt",
"tlbi_rvae2is_xt",
"tlbi_rvale2is_xt",
"tlbi_rvae3is_xt",
"tlbi_rvale3is_xt",
"tlbi_rvae1os_xt",
"tlbi_rvaae1os_xt",
"tlbi_rvale1os_xt",
"tlbi_rvaale1os_xt",
"tlbi_ripas2e1os_xt",
"tlbi_ripas2le1os_xt",
"tlbi_rvae2os_xt",
"tlbi_rvale2os_xt",
"tlbi_rvae3os_xt",
"tlbi_rvale3os_xt",
"tlbi_vae3",
"tlbi_vale3",
"tlbi_rvae1",
"tlbi_rvaae1",
"tlbi_rvale1",
"tlbi_rvaale1",
"tlbi_ripas2e1",
"tlbi_ripas2le1",
"tlbi_rvae2",
"tlbi_rvale2",
"tlbi_rvae3",
"tlbi_rvale3",
"tlbi_rvae1is",
"tlbi_rvaae1is",
"tlbi_rvale1is",
"tlbi_rvaale1is",
"tlbi_ripas2e1is",
"tlbi_ripas2le1is",
"tlbi_rvae2is",
"tlbi_rvale2is",
"tlbi_rvae3is",
"tlbi_rvale3is",
"tlbi_rvae1os",
"tlbi_rvaae1os",
"tlbi_rvale1os",
"tlbi_rvaale1os",
"tlbi_ripas2e1os",
"tlbi_ripas2le1os",
"tlbi_rvae2os",
"tlbi_rvale2os",
"tlbi_rvae3os",
"tlbi_rvale3os",
"pmintenset_el1",
"pmintenclr_el1",
"pmcr_el0",

44
src/arch/arm/tracers/tarmac_parser.cc
View File

@@ -625,37 +625,37 @@ TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = {
{ "at_s1e3r_xt", MISCREG_AT_S1E3R_Xt },
{ "at_s1e3w_xt", MISCREG_AT_S1E3W_Xt },
{ "tlbi_vmalle1is", MISCREG_TLBI_VMALLE1IS },
{ "tlbi_vae1is_xt", MISCREG_TLBI_VAE1IS_Xt },
{ "tlbi_aside1is_xt", MISCREG_TLBI_ASIDE1IS_Xt },
{ "tlbi_vaae1is_xt", MISCREG_TLBI_VAAE1IS_Xt },
{ "tlbi_vale1is_xt", MISCREG_TLBI_VALE1IS_Xt },
{ "tlbi_vaale1is_xt", MISCREG_TLBI_VAALE1IS_Xt },
{ "tlbi_vae1is", MISCREG_TLBI_VAE1IS },
{ "tlbi_aside1is", MISCREG_TLBI_ASIDE1IS },
{ "tlbi_vaae1is", MISCREG_TLBI_VAAE1IS },
{ "tlbi_vale1is", MISCREG_TLBI_VALE1IS },
{ "tlbi_vaale1is", MISCREG_TLBI_VAALE1IS },
{ "tlbi_vmalle1", MISCREG_TLBI_VMALLE1 },
{ "tlbi_vae1_xt", MISCREG_TLBI_VAE1_Xt },
{ "tlbi_aside1_xt", MISCREG_TLBI_ASIDE1_Xt },
{ "tlbi_vaae1_xt", MISCREG_TLBI_VAAE1_Xt },
{ "tlbi_vale1_xt", MISCREG_TLBI_VALE1_Xt },
{ "tlbi_vaale1_xt", MISCREG_TLBI_VAALE1_Xt },
{ "tlbi_ipas2e1is_xt", MISCREG_TLBI_IPAS2E1IS_Xt },
{ "tlbi_ipas2le1is_xt", MISCREG_TLBI_IPAS2LE1IS_Xt },
{ "tlbi_vae1", MISCREG_TLBI_VAE1 },
{ "tlbi_aside1", MISCREG_TLBI_ASIDE1 },
{ "tlbi_vaae1", MISCREG_TLBI_VAAE1 },
{ "tlbi_vale1", MISCREG_TLBI_VALE1 },
{ "tlbi_vaale1", MISCREG_TLBI_VAALE1 },
{ "tlbi_ipas2e1is", MISCREG_TLBI_IPAS2E1IS },
{ "tlbi_ipas2le1is", MISCREG_TLBI_IPAS2LE1IS },
{ "tlbi_alle2is", MISCREG_TLBI_ALLE2IS },
{ "tlbi_vae2is_xt", MISCREG_TLBI_VAE2IS_Xt },
{ "tlbi_vae2is", MISCREG_TLBI_VAE2IS },
{ "tlbi_alle1is", MISCREG_TLBI_ALLE1IS },
{ "tlbi_vale2is_xt", MISCREG_TLBI_VALE2IS_Xt },
{ "tlbi_vale2is", MISCREG_TLBI_VALE2IS },
{ "tlbi_vmalls12e1is", MISCREG_TLBI_VMALLS12E1IS },
{ "tlbi_ipas2e1_xt", MISCREG_TLBI_IPAS2E1_Xt },
{ "tlbi_ipas2le1_xt", MISCREG_TLBI_IPAS2LE1_Xt },
{ "tlbi_ipas2e1", MISCREG_TLBI_IPAS2E1 },
{ "tlbi_ipas2le1", MISCREG_TLBI_IPAS2LE1 },
{ "tlbi_alle2", MISCREG_TLBI_ALLE2 },
{ "tlbi_vae2_xt", MISCREG_TLBI_VAE2_Xt },
{ "tlbi_vae2", MISCREG_TLBI_VAE2 },
{ "tlbi_alle1", MISCREG_TLBI_ALLE1 },
{ "tlbi_vale2_xt", MISCREG_TLBI_VALE2_Xt },
{ "tlbi_vale2", MISCREG_TLBI_VALE2 },
{ "tlbi_vmalls12e1", MISCREG_TLBI_VMALLS12E1 },
{ "tlbi_alle3is", MISCREG_TLBI_ALLE3IS },
{ "tlbi_vae3is_xt", MISCREG_TLBI_VAE3IS_Xt },
{ "tlbi_vale3is_xt", MISCREG_TLBI_VALE3IS_Xt },
{ "tlbi_vae3is", MISCREG_TLBI_VAE3IS },
{ "tlbi_vale3is", MISCREG_TLBI_VALE3IS },
{ "tlbi_alle3", MISCREG_TLBI_ALLE3 },
{ "tlbi_vae3_xt", MISCREG_TLBI_VAE3_Xt },
{ "tlbi_vale3_xt", MISCREG_TLBI_VALE3_Xt },
{ "tlbi_vae3", MISCREG_TLBI_VAE3 },
{ "tlbi_vale3", MISCREG_TLBI_VALE3 },
{ "pmintenset_el1", MISCREG_PMINTENSET_EL1 },
{ "pmintenclr_el1", MISCREG_PMINTENCLR_EL1 },
{ "pmcr_el0", MISCREG_PMCR_EL0 },