stdlib,configs: Config added for RISCV boot-test using stdlib.

This change adds a config file to boot Ubuntu-20.04 using RISCV ISA
using gem5 stdlib. It also adds a new test for the same.

Signed-off-by: Kaustav Goswami <kggoswami@ucdavis.edu>
Change-Id: Id2b5e46e7ba9e3c4701c97330406537dffa44479
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53024
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

configs/example/gem5_library/riscv-ubuntu-run.py

@@ -0,0 +1,146 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This script shows an example of running a full system RISCV Ubuntu boot
+simulation using the gem5 library. This simulation boots Ubuntu 20.04 using
+2 TIMING CPU cores. The simulation ends when the startup is completed
+successfully.
+
+Usage
+-----
+
+```
+scons build/RISCV/gem5.opt
+./build/RISCV/gem5.opt \
+    configs/example/gem5_library/riscv-ubuntu-run.py
+```
+"""
+
+import m5
+from m5.objects import Root
+
+from gem5.utils.requires import requires
+from gem5.components.boards.riscv_board import RiscvBoard
+from gem5.components.memory import DualChannelDDR4_2400
+from gem5.components.processors.simple_processor import (
+    SimpleProcessor,
+)
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.isas import ISA
+from gem5.coherence_protocol import CoherenceProtocol
+from gem5.resources.resource import Resource
+
+# This runs a check to ensure the gem5 binary is compiled for RISCV.
+
+requires(
+    isa_required=ISA.RISCV,
+)
+
+# With RISCV, we use simple caches.
+from gem5.components.cachehierarchies.classic\
+    .private_l1_private_l2_cache_hierarchy import (
+    PrivateL1PrivateL2CacheHierarchy,
+)
+# Here we setup the parameters of the l1 and l2 caches.
+cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
+    l1d_size="16kB",
+    l1i_size="16kB",
+    l2_size="256kB",
+)
+
+# Memory: Dual Channel DDR4 2400 DRAM device.
+
+memory = DualChannelDDR4_2400(size = "3GB")
+
+# Here we setup the processor. We use a simple processor.
+processor = SimpleProcessor(
+    cpu_type=CPUTypes.TIMING,
+    num_cores=2,
+)
+
+# Here we setup the board. The RiscvBoard allows for Full-System RISCV
+# simulations.
+board = RiscvBoard(
+    clk_freq="3GHz",
+    processor=processor,
+    memory=memory,
+    cache_hierarchy=cache_hierarchy,
+)
+
+# Here we set the Full System workload.
+
+# The `set_kernel_disk_workload` function for the RiscvBoard accepts a
+# RISCV bootloader and a disk image. Once the system successfully boots, it
+# encounters an `m5_exit instruction encountered`. We stop the simulation then.
+# When the simulation has ended you may inspect `m5out/system.pc.com_1.device`
+# to see the stdout.
+
+board.set_kernel_disk_workload(
+    # The RISCV bootloader will be automatically downloaded to the
+    # `~/.cache/gem5` directory if not already present.
+    # The riscv-ubuntu boot-test was tested with riscv-bootloader-5.10
+    kernel=Resource(
+        "riscv-bootloader-vmlinux-5.10",
+    ),
+    # The RISCV ubuntu image will be automatically downloaded to the
+    # `~/.cache/gem5` directory if not already present.
+    disk_image=Resource(
+        "riscv-ubuntu-20.04-img",
+    ),
+)
+
+root = Root(full_system=True, system=board)
+
+m5.instantiate()
+
+# We simulate the system till we encounter `m5_exit instruction encountered`.
+
+exit_event = m5.simulate()
+
+# We check whether the simulation ended with `m5_exit instruction encountered`
+
+if exit_event.getCause() == "m5_exit instruction encountered":
+    # We acknowledge the user that the boot was successful.
+
+    print("Successfully completed booting!")
+else:
+    # `m5_exit instruction encountered` was never encountered. We exit the
+    # program unsuccessfully.
+
+    print("The startup was not completed successfully!",)
+    print(
+    "Exiting @ tick {} because {}."\
+        .format(m5.curTick(), exit_event.getCause())
+    )
+    exit(-1)
+
+# We are done with the simulation. We exit the program now.
+
+print(
+"Exiting @ tick {} because {}."\
+    .format(m5.curTick(), exit_event.getCause())
+)