configs, dev, learning-gem5, python, tests: more clarification

This commit contains the rest of the base 2 vs base 10 cache/memory
size clarifications. It also changes the warning message to use
warn(). With these changes, the warning message should now no
longer show up during a fresh compilation of gem5.

Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631

src/python/gem5/components/boards/riscv_board.py

@@ -174,9 +174,9 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload):
             ]
 
             # PCI
-            self.bridge.ranges.append(AddrRange(0x2F000000, size="16MB"))
-            self.bridge.ranges.append(AddrRange(0x30000000, size="256MB"))
-            self.bridge.ranges.append(AddrRange(0x40000000, size="512MB"))
+            self.bridge.ranges.append(AddrRange(0x2F000000, size="16MiB"))
+            self.bridge.ranges.append(AddrRange(0x30000000, size="256MiB"))
+            self.bridge.ranges.append(AddrRange(0x40000000, size="512MiB"))
 
     def _setup_pma(self) -> None:
         """Set the PMA devices on each core."""
@@ -187,9 +187,9 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload):
         ]
 
         # PCI
-        uncacheable_range.append(AddrRange(0x2F000000, size="16MB"))
-        uncacheable_range.append(AddrRange(0x30000000, size="256MB"))
-        uncacheable_range.append(AddrRange(0x40000000, size="512MB"))
+        uncacheable_range.append(AddrRange(0x2F000000, size="16MiB"))
+        uncacheable_range.append(AddrRange(0x30000000, size="256MiB"))
+        uncacheable_range.append(AddrRange(0x40000000, size="512MiB"))
 
         # TODO: Not sure if this should be done per-core like in the example
         for cpu in self.get_processor().get_cores():

src/python/gem5/components/memory/dram_interfaces/ddr5.py

@@ -86,10 +86,10 @@ class DDR5_4400_4x8(DRAMInterface):
     # RRD_S (different bank group) : 8nCK
     tRRD = "3.632ns"
 
-    # RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KB page
+    # RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KiB page
     tRRD_L = "5ns"
 
-    # tFAW for 1KB page is MAX(32nCK, 14.545ns)
+    # tFAW for 1KiB page is MAX(32nCK, 14.545ns)
     tXAW = "14.545ns"
     activation_limit = 4
 
@@ -194,10 +194,10 @@ class DDR5_6400_4x8(DDR5_4400_4x8):
     # RRD_S (different bank group) : 8nCK
     tRRD = "2.496ns"
 
-    # RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KB page
+    # RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KiB page
     tRRD_L = "5ns"
 
-    # tFAW for 1KB page is MAX(32 CK, 10.00ns)
+    # tFAW for 1KiB page is MAX(32 CK, 10.00ns)
     tXAW = "10ns"
 
     # Rd/Wr turnaround timings
@@ -254,7 +254,7 @@ class DDR5_8400_4x8(DDR5_4400_4x8):
     # RRD_S (different bank group) : 8nCK
     tRRD = "1.904ns"
 
-    # tFAW for 1KB page is MAX(32 CK, 10.00ns)
+    # tFAW for 1KiB page is MAX(32 CK, 10.00ns)
     tXAW = "10ns"
 
     # Rd/Wr turnaround timings

src/python/gem5/components/processors/complex_generator.py

@@ -58,7 +58,7 @@ class ComplexGenerator(AbstractGenerator):
     def add_linear(
         self,
         duration: str = "1ms",
-        rate: str = "100GB/s",
+        rate: str = "100GiB/s",
         block_size: int = 64,
         min_addr: int = 0,
         max_addr: int = 32768,
@@ -99,7 +99,7 @@ class ComplexGenerator(AbstractGenerator):
     def add_random(
         self,
         duration: str = "1ms",
-        rate: str = "100GB/s",
+        rate: str = "100GiB/s",
         block_size: int = 64,
         min_addr: int = 0,
         max_addr: int = 32768,

src/python/gem5/components/processors/linear_generator.py

@@ -39,7 +39,7 @@ class LinearGenerator(AbstractGenerator):
         self,
         num_cores: int = 1,
         duration: str = "1ms",
-        rate: str = "100GB/s",
+        rate: str = "100GiB/s",
         block_size: int = 64,
         min_addr: int = 0,
         max_addr: int = 32768,

src/python/gem5/components/processors/random_generator.py

@@ -38,7 +38,7 @@ class RandomGenerator(AbstractGenerator):
         self,
         num_cores: int = 1,
         duration: str = "1ms",
-        rate: str = "100GB/s",
+        rate: str = "100GiB/s",
         block_size: int = 64,
         min_addr: int = 0,
         max_addr: int = 32768,

src/python/gem5/components/processors/strided_generator.py

@@ -40,7 +40,7 @@ class StridedGenerator(AbstractGenerator):
         self,
         num_cores: int = 1,
         duration: str = "1ms",
-        rate: str = "100GB/s",
+        rate: str = "100GiB/s",
         block_size: int = 64,
         superblock_size: int = 64,
         stride_size: Optional[int] = None,

src/python/m5/SimObject.py

@@ -92,7 +92,7 @@ from m5.util.pybind import *
 # object, either using keyword assignment in the constructor or in
 # separate assignment statements.  For example:
 #
-# cache = BaseCache(size='64KB')
+# cache = BaseCache(size='64KiB')
 # cache.hit_latency = 3
 # cache.assoc = 8
 #

src/python/m5/util/convert.py

@@ -270,9 +270,11 @@ def toMemorySize(value):
         and value[-2] in binary_prefixes.keys()
         and not "i" in value
     ):
-        print(
-            f"warn: Base 10 memory/cache size {value} will be cast to base 2"
-            + f" size {value[0:-2]}{value[-2].upper()}i{value[-1]}"
+        from m5.util import warn
+
+        warn(
+            f"Base 10 memory/cache size {value} will be cast to base 2"
+            + f" size {value[0:-2]}{value[-2].upper()}i{value[-1]}."
         )
     return toBinaryInteger(value, "memory size", "B")