configs, dev, learning-gem5, python, tests: more clarification

This commit contains the rest of the base 2 vs base 10 cache/memory
size clarifications. It also changes the warning message to use
warn(). With these changes, the warning message should now no
longer show up during a fresh compilation of gem5.

Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631

src/dev/arm/RealView.py

@@ -1189,8 +1189,8 @@ class VExpress_GEM5_Base(RealView):
     Memory map:
        0x00000000-0x03ffffff: Boot memory (CS0)
        0x04000000-0x07ffffff: Trusted Memory/Reserved
-            0x04000000-0x0403FFFF: 256kB Trusted SRAM
-            0x06000000-0x07ffffff: 32MB Trusted DRAM
+            0x04000000-0x0403FFFF: 256KiB Trusted SRAM
+            0x06000000-0x07ffffff: 32MiB Trusted DRAM
        0x08000000-0x0bffffff: NOR FLASH0 (CS0 alias)
        0x0c000000-0x0fffffff: NOR FLASH1 (Off-chip, CS4)
        0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
@@ -1316,7 +1316,7 @@ class VExpress_GEM5_Base(RealView):
     # Trusted DRAM
     # TODO: preventing access from unsecure world to the trusted RAM
     trusted_dram = SimpleMemory(
-        range=AddrRange(0x06000000, size="32MB"), conf_table_reported=False
+        range=AddrRange(0x06000000, size="32MiB"), conf_table_reported=False
     )
     # Non-Trusted SRAM
     non_trusted_sram = MmioSRAM(
@@ -1454,7 +1454,7 @@ class VExpress_GEM5_Base(RealView):
 
     # VRAM
     vram = SimpleMemory(
-        range=AddrRange(0x18000000, size="32MB"), conf_table_reported=False
+        range=AddrRange(0x18000000, size="32MiB"), conf_table_reported=False
     )
 
     def _off_chip_devices(self):

src/dev/riscv/HiFive.py

@@ -183,7 +183,7 @@ class HiFive(HiFiveBase):
     # PCI
     pci_host = GenericRiscvPciHost(
         conf_base=0x30000000,
-        conf_size="256MB",
+        conf_size="256MiB",
         conf_device_bits=12,
         pci_pio_base=0x2F000000,
         pci_mem_base=0x40000000,