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configs, dev, learning-gem5, python, tests: more clarification

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This commit contains the rest of the base 2 vs base 10 cache/memory
size clarifications. It also changes the warning message to use
warn(). With these changes, the warning message should now no
longer show up during a fresh compilation of gem5.

Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631
This commit is contained in:
Erin Le
2024-08-24 01:01:04 +00:00
committed by Erin (Jianghua) Le
parent 28453a0e3e
commit e1db67c4bd
87 changed files with 255 additions and 249 deletions
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8
src/dev/arm/RealView.py
View File

@@ -1189,8 +1189,8 @@ class VExpress_GEM5_Base(RealView):
Memory map:
0x00000000-0x03ffffff: Boot memory (CS0)
0x04000000-0x07ffffff: Trusted Memory/Reserved
0x04000000-0x0403FFFF: 256kB Trusted SRAM
0x06000000-0x07ffffff: 32MB Trusted DRAM
0x04000000-0x0403FFFF: 256KiB Trusted SRAM
0x06000000-0x07ffffff: 32MiB Trusted DRAM
0x08000000-0x0bffffff: NOR FLASH0 (CS0 alias)
0x0c000000-0x0fffffff: NOR FLASH1 (Off-chip, CS4)
0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
@@ -1316,7 +1316,7 @@ class VExpress_GEM5_Base(RealView):
# Trusted DRAM
# TODO: preventing access from unsecure world to the trusted RAM
trusted_dram = SimpleMemory(
range=AddrRange(0x06000000, size="32MB"), conf_table_reported=False
range=AddrRange(0x06000000, size="32MiB"), conf_table_reported=False
)
# Non-Trusted SRAM
non_trusted_sram = MmioSRAM(
@@ -1454,7 +1454,7 @@ class VExpress_GEM5_Base(RealView):
# VRAM
vram = SimpleMemory(
range=AddrRange(0x18000000, size="32MB"), conf_table_reported=False
range=AddrRange(0x18000000, size="32MiB"), conf_table_reported=False
)
def _off_chip_devices(self):

2
src/dev/riscv/HiFive.py
View File

@@ -183,7 +183,7 @@ class HiFive(HiFiveBase):
# PCI
pci_host = GenericRiscvPciHost(
conf_base=0x30000000,
conf_size="256MB",
conf_size="256MiB",
conf_device_bits=12,
pci_pio_base=0x2F000000,
pci_mem_base=0x40000000,

4
src/learning_gem5/part2/HelloObject.py
View File

@@ -47,8 +47,8 @@ class GoodbyeObject(SimObject):
cxx_class = "gem5::GoodbyeObject"
buffer_size = Param.MemorySize(
"1kB", "Size of buffer to fill with goodbye"
"1KiB", "Size of buffer to fill with goodbye"
)
write_bandwidth = Param.MemoryBandwidth(
"100MB/s", "Bandwidth to fill the buffer"
"100MiB/s", "Bandwidth to fill the buffer"
)

2
src/learning_gem5/part2/SimpleCache.py
View File

@@ -41,6 +41,6 @@ class SimpleCache(ClockedObject):
latency = Param.Cycles(1, "Cycles taken on a hit or to resolve a miss")
size = Param.MemorySize("16kB", "The size of the cache")
size = Param.MemorySize("16KiB", "The size of the cache")
system = Param.System(Parent.any, "The system this cache is part of")

16
src/mem/DRAMInterface.py
View File

@@ -294,7 +294,7 @@ class DDR3_1600_8x8(DRAMInterface):
# DDR3 is a BL8 device
burst_length = 8
# Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
# Each device has a page (row buffer) size of 1 Kibibyte (1KiB columns x8)
device_rowbuffer_size = "1KiB"
# 8x8 configuration, so 8 devices
@@ -700,7 +700,7 @@ class LPDDR2_S4_1066_1x32(DRAMInterface):
# LPDDR2_S4 is a BL4 and BL8 device
burst_length = 8
# Each device has a page (row buffer) size of 1KB
# Each device has a page (row buffer) size of 1KiB
# (this depends on the memory density)
device_rowbuffer_size = "1KiB"
@@ -1276,7 +1276,7 @@ class DDR5_4400_4x8(DRAMInterface):
burst_length = 16
# Each device has a page (row buffer) size of 256B
# Four devices lead to a page size of 1KB
# Four devices lead to a page size of 1KiB
device_rowbuffer_size = "256B"
# 4Gbx8 configuration
@@ -1312,10 +1312,10 @@ class DDR5_4400_4x8(DRAMInterface):
# RRD_S (different bank group) : 8nCK
tRRD = "3.632ns"
# RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KB page
# RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KiB page
tRRD_L = "5ns"
# tFAW for 1KB page is MAX(32nCK, 14.545ns)
# tFAW for 1KiB page is MAX(32nCK, 14.545ns)
tXAW = "14.545ns"
activation_limit = 4
@@ -1420,10 +1420,10 @@ class DDR5_6400_4x8(DDR5_4400_4x8):
# RRD_S (different bank group) : 8nCK
tRRD = "2.496ns"
# RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KB page
# RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KiB page
tRRD_L = "5ns"
# tFAW for 1KB page is MAX(32 CK, 10.00ns)
# tFAW for 1KiB page is MAX(32 CK, 10.00ns)
tXAW = "10ns"
# Rd/Wr turnaround timings
@@ -1480,7 +1480,7 @@ class DDR5_8400_4x8(DDR5_4400_4x8):
# RRD_S (different bank group) : 8nCK
tRRD = "1.904ns"
# tFAW for 1KB page is MAX(32 CK, 10.00ns)
# tFAW for 1KiB page is MAX(32 CK, 10.00ns)
tXAW = "10ns"
# Rd/Wr turnaround timings

12
src/python/gem5/components/boards/riscv_board.py
View File

@@ -174,9 +174,9 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload):
]
# PCI
self.bridge.ranges.append(AddrRange(0x2F000000, size="16MB"))
self.bridge.ranges.append(AddrRange(0x30000000, size="256MB"))
self.bridge.ranges.append(AddrRange(0x40000000, size="512MB"))
self.bridge.ranges.append(AddrRange(0x2F000000, size="16MiB"))
self.bridge.ranges.append(AddrRange(0x30000000, size="256MiB"))
self.bridge.ranges.append(AddrRange(0x40000000, size="512MiB"))
def _setup_pma(self) -> None:
"""Set the PMA devices on each core."""
@@ -187,9 +187,9 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload):
]
# PCI
uncacheable_range.append(AddrRange(0x2F000000, size="16MB"))
uncacheable_range.append(AddrRange(0x30000000, size="256MB"))
uncacheable_range.append(AddrRange(0x40000000, size="512MB"))
uncacheable_range.append(AddrRange(0x2F000000, size="16MiB"))
uncacheable_range.append(AddrRange(0x30000000, size="256MiB"))
uncacheable_range.append(AddrRange(0x40000000, size="512MiB"))
# TODO: Not sure if this should be done per-core like in the example
for cpu in self.get_processor().get_cores():

10
src/python/gem5/components/memory/dram_interfaces/ddr5.py
View File

@@ -86,10 +86,10 @@ class DDR5_4400_4x8(DRAMInterface):
# RRD_S (different bank group) : 8nCK
tRRD = "3.632ns"
# RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KB page
# RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KiB page
tRRD_L = "5ns"
# tFAW for 1KB page is MAX(32nCK, 14.545ns)
# tFAW for 1KiB page is MAX(32nCK, 14.545ns)
tXAW = "14.545ns"
activation_limit = 4
@@ -194,10 +194,10 @@ class DDR5_6400_4x8(DDR5_4400_4x8):
# RRD_S (different bank group) : 8nCK
tRRD = "2.496ns"
# RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KB page
# RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KiB page
tRRD_L = "5ns"
# tFAW for 1KB page is MAX(32 CK, 10.00ns)
# tFAW for 1KiB page is MAX(32 CK, 10.00ns)
tXAW = "10ns"
# Rd/Wr turnaround timings
@@ -254,7 +254,7 @@ class DDR5_8400_4x8(DDR5_4400_4x8):
# RRD_S (different bank group) : 8nCK
tRRD = "1.904ns"
# tFAW for 1KB page is MAX(32 CK, 10.00ns)
# tFAW for 1KiB page is MAX(32 CK, 10.00ns)
tXAW = "10ns"
# Rd/Wr turnaround timings

4
src/python/gem5/components/processors/complex_generator.py
View File

@@ -58,7 +58,7 @@ class ComplexGenerator(AbstractGenerator):
def add_linear(
self,
duration: str = "1ms",
rate: str = "100GB/s",
rate: str = "100GiB/s",
block_size: int = 64,
min_addr: int = 0,
max_addr: int = 32768,
@@ -99,7 +99,7 @@ class ComplexGenerator(AbstractGenerator):
def add_random(
self,
duration: str = "1ms",
rate: str = "100GB/s",
rate: str = "100GiB/s",
block_size: int = 64,
min_addr: int = 0,
max_addr: int = 32768,

2
src/python/gem5/components/processors/linear_generator.py
View File

@@ -39,7 +39,7 @@ class LinearGenerator(AbstractGenerator):
self,
num_cores: int = 1,
duration: str = "1ms",
rate: str = "100GB/s",
rate: str = "100GiB/s",
block_size: int = 64,
min_addr: int = 0,
max_addr: int = 32768,

2
src/python/gem5/components/processors/random_generator.py
View File

@@ -38,7 +38,7 @@ class RandomGenerator(AbstractGenerator):
self,
num_cores: int = 1,
duration: str = "1ms",
rate: str = "100GB/s",
rate: str = "100GiB/s",
block_size: int = 64,
min_addr: int = 0,
max_addr: int = 32768,

2
src/python/gem5/components/processors/strided_generator.py
View File

@@ -40,7 +40,7 @@ class StridedGenerator(AbstractGenerator):
self,
num_cores: int = 1,
duration: str = "1ms",
rate: str = "100GB/s",
rate: str = "100GiB/s",
block_size: int = 64,
superblock_size: int = 64,
stride_size: Optional[int] = None,

2
src/python/m5/SimObject.py
View File

@@ -92,7 +92,7 @@ from m5.util.pybind import *
# object, either using keyword assignment in the constructor or in
# separate assignment statements. For example:
#
# cache = BaseCache(size='64KB')
# cache = BaseCache(size='64KiB')
# cache.hit_latency = 3
# cache.assoc = 8
#

8
src/python/m5/util/convert.py
View File

@@ -270,9 +270,11 @@ def toMemorySize(value):
and value[-2] in binary_prefixes.keys()
and not "i" in value
):
print(
f"warn: Base 10 memory/cache size {value} will be cast to base 2"
+ f" size {value[0:-2]}{value[-2].upper()}i{value[-1]}"
from m5.util import warn
warn(
f"Base 10 memory/cache size {value} will be cast to base 2"
+ f" size {value[0:-2]}{value[-2].upper()}i{value[-1]}."
)
return toBinaryInteger(value, "memory size", "B")