Merge zizzer:/bk/m5

into  zeep.eecs.umich.edu:/z/saidi/work/m5.head

cpu/simple/cpu.cc:
    remove initCPU from constructor
dev/alpha_console.cc:
    we are panicing, so no need to return a fault

--HG--
extra : convert_revision : 72389ea0c96e91a55f35b884200325224bfb6ed9
This commit is contained in:
Ali Saidi
2006-02-23 15:06:06 -05:00
8 changed files with 88 additions and 75 deletions

View File

@@ -33,7 +33,7 @@
* System Console Memory Mapped Register Definition
*/
#define ALPHA_ACCESS_VERSION (1303)
#define ALPHA_ACCESS_VERSION (1305)
#ifdef CONSOLE
typedef unsigned uint32_t;
@@ -67,9 +67,7 @@ struct AlphaAccess
uint64_t inputChar; // 68: Placeholder for input
// MP boot
uint64_t bootStrapImpure; // 70:
uint32_t bootStrapCPU; // 78:
uint32_t align2; // 7C: Dummy placeholder for alignment
uint64_t cpuStack[64]; // 70:
};
#endif // __ALPHA_ACCESS_H__

View File

@@ -81,9 +81,7 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
alphaAccess->diskOperation = 0;
alphaAccess->outputChar = 0;
alphaAccess->inputChar = 0;
alphaAccess->bootStrapImpure = 0;
alphaAccess->bootStrapCPU = 0;
alphaAccess->align2 = 0;
bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack));
system->setAlphaAccess(addr);
}
@@ -123,9 +121,6 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
case offsetof(AlphaAccess, numCPUs):
*(uint32_t*)data = alphaAccess->numCPUs;
break;
case offsetof(AlphaAccess, bootStrapCPU):
*(uint32_t*)data = alphaAccess->bootStrapCPU;
break;
case offsetof(AlphaAccess, intrClockFrequency):
*(uint32_t*)data = alphaAccess->intrClockFrequency;
break;
@@ -176,11 +171,14 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
case offsetof(AlphaAccess, outputChar):
*(uint64_t*)data = alphaAccess->outputChar;
break;
case offsetof(AlphaAccess, bootStrapImpure):
*(uint64_t*)data = alphaAccess->bootStrapImpure;
break;
default:
panic("Unknown 64bit access, %#x\n", daddr);
int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
sizeof(alphaAccess->cpuStack[0]);
if (cpunum >= 0 && cpunum < 64)
*(uint64_t*)data = alphaAccess->cpuStack[cpunum];
else
panic("Unknown 64bit access, %#x\n", daddr);
}
break;
default:
@@ -240,24 +238,18 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
console->out((char)(val & 0xff));
break;
case offsetof(AlphaAccess, bootStrapImpure):
alphaAccess->bootStrapImpure = val;
break;
case offsetof(AlphaAccess, bootStrapCPU):
warn("%d: Trying to launch another CPU!", curTick);
assert(val > 0 && "Must not access primary cpu");
other_xc = req->xc->system->execContexts[val];
other_xc->regs.intRegFile[16] = val;
other_xc->regs.ipr[TheISA::IPR_PALtemp16] = val;
other_xc->regs.intRegFile[0] = val;
other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure;
other_xc->activate(); //Start the cpu
break;
default:
return MachineCheckFault;
int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
sizeof(alphaAccess->cpuStack[0]);
warn("%d: Trying to launch CPU number %d!", curTick, cpunum);
assert(val > 0 && "Must not access primary cpu");
if (cpunum >= 0 && cpunum < 64)
alphaAccess->cpuStack[cpunum] = val;
else
panic("Unknown 64bit access, %#x\n", daddr);
}
return NoFault;
@@ -288,8 +280,7 @@ AlphaConsole::Access::serialize(ostream &os)
SERIALIZE_SCALAR(diskOperation);
SERIALIZE_SCALAR(outputChar);
SERIALIZE_SCALAR(inputChar);
SERIALIZE_SCALAR(bootStrapImpure);
SERIALIZE_SCALAR(bootStrapCPU);
SERIALIZE_ARRAY(cpuStack,64);
}
void
@@ -311,8 +302,7 @@ AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(diskOperation);
UNSERIALIZE_SCALAR(outputChar);
UNSERIALIZE_SCALAR(inputChar);
UNSERIALIZE_SCALAR(bootStrapImpure);
UNSERIALIZE_SCALAR(bootStrapCPU);
UNSERIALIZE_ARRAY(cpuStack, 64);
}
void

View File

@@ -96,7 +96,7 @@ class AlphaConsole : public PioDevice
BaseCPU *cpu;
Addr addr;
static const Addr size = 0x80; // equal to sizeof(alpha_access);
static const Addr size = sizeof(struct AlphaAccess);
public:
/** Standard Constructor */