From e097c4fb188fafc9cd2253500ab2d056da886c9c Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 13 May 2011 17:27:01 -0500 Subject: [PATCH] ARM: Remove the saturating (Q) condition code from the renamed register. Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR miscreg and adds a allows setting it in a similar way to the FP saturating registers. This removes a dependency in instructions that don't write, but need to preserve the Q bit. --- src/arch/arm/faults.cc | 1 - src/arch/arm/intregs.hh | 1 - src/arch/arm/isa.cc | 9 +++++++++ src/arch/arm/isa/insts/data.isa | 5 ++--- src/arch/arm/isa/insts/ldr.isa | 2 +- src/arch/arm/isa/insts/macromem.isa | 4 +--- src/arch/arm/isa/insts/misc.isa | 26 +++++++++----------------- src/arch/arm/isa/insts/mult.isa | 2 +- src/arch/arm/isa/operands.isa | 2 +- src/arch/arm/miscregs.hh | 7 ++++--- src/arch/arm/nativetrace.cc | 1 - 11 files changed, 28 insertions(+), 32 deletions(-) diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 4b58a7144e..e7e78e1780 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -108,7 +108,6 @@ ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst) CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | tc->readIntReg(INTREG_CONDCODES_F) | - tc->readIntReg(INTREG_CONDCODES_Q) | tc->readIntReg(INTREG_CONDCODES_GE); Addr curPc M5_VAR_USED = tc->pcState().pc(); ITSTATE it = tc->pcState().itstate(); diff --git a/src/arch/arm/intregs.hh b/src/arch/arm/intregs.hh index 412efc92b1..000c6306d2 100644 --- a/src/arch/arm/intregs.hh +++ b/src/arch/arm/intregs.hh @@ -113,7 +113,6 @@ enum IntRegIndex INTREG_UREG1, INTREG_UREG2, INTREG_CONDCODES_F, - INTREG_CONDCODES_Q, INTREG_CONDCODES_GE, INTREG_FPCONDCODES, diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 0db9414625..27218bca86 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -216,6 +216,8 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) warn("Not doing anything for read to miscreg %s\n", miscRegName[misc_reg]); break; + case MISCREG_CPSR_Q: + panic("shouldn't be reading this register seperately\n"); case MISCREG_FPSCR_QC: return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; case MISCREG_FPSCR_EXC: @@ -316,6 +318,13 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); } break; + case MISCREG_CPSR_Q: + { + assert(!(newVal & ~CpsrMaskQ)); + newVal = miscRegs[MISCREG_CPSR] | newVal; + misc_reg = MISCREG_CPSR; + } + break; case MISCREG_FPSCR_QC: { newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa index a6d4c7daa0..1a239f48ba 100644 --- a/src/arch/arm/isa/insts/data.isa +++ b/src/arch/arm/isa/insts/data.isa @@ -48,7 +48,7 @@ let {{ ''' calcQCode = ''' - CondCodesQ = CondCodesQ | ((resTemp & 1) << 27); + CpsrQ = (resTemp & 1) << 27; ''' calcCcCode = ''' @@ -239,11 +239,10 @@ let {{ code += ''' SCTLR sctlr = Sctlr; uint32_t newCpsr = - cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE, + cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, Spsr, 0xF, true, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; CondCodesF = CondCodesMaskF & newCpsr; - CondCodesQ = CondCodesMaskQ & newCpsr; CondCodesGE = CondCodesMaskGE & newCpsr; NextThumb = ((CPSR)newCpsr).t; NextJazelle = ((CPSR)newCpsr).j; diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index bf8034a9e4..9211983d40 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -106,7 +106,7 @@ let {{ wbDiff = 8 accCode = ''' CPSR cpsr = Cpsr; - URc = cpsr | CondCodesF | CondCodesQ | CondCodesGE; + URc = cpsr | CondCodesF | CondCodesGE; URa = cSwap(Mem.ud, cpsr.e); URb = cSwap(Mem.ud >> 32, cpsr.e); ''' diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 5007c85e57..8523b840ce 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -90,11 +90,10 @@ let {{ CPSR cpsr = Cpsr; SCTLR sctlr = Sctlr; uint32_t newCpsr = - cpsrWriteByInstr(cpsr | CondCodesF | CondCodesQ | CondCodesGE, + cpsrWriteByInstr(cpsr | CondCodesF | CondCodesGE, Spsr, 0xF, true, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; CondCodesF = CondCodesMaskF & newCpsr; - CondCodesQ = CondCodesMaskQ & newCpsr; CondCodesGE = CondCodesMaskGE & newCpsr; IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0); NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC) @@ -635,7 +634,6 @@ let {{ NextItState = ((((CPSR)URb).it2 << 2) & 0xFC) | (((CPSR)URb).it1 & 0x3); CondCodesF = CondCodesMaskF & newCpsr; - CondCodesQ = CondCodesMaskQ & newCpsr; CondCodesGE = CondCodesMaskGE & newCpsr; ''' diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index a084777035..c223842127 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -61,7 +61,7 @@ let {{ header_output = decoder_output = exec_output = "" mrsCpsrCode = ''' - Dest = (Cpsr | CondCodesF | CondCodesQ | CondCodesGE) & 0xF8FF03DF + Dest = (Cpsr | CondCodesF | CondCodesGE) & 0xF8FF03DF ''' mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", @@ -84,11 +84,10 @@ let {{ msrCpsrRegCode = ''' SCTLR sctlr = Sctlr; uint32_t newCpsr = - cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE, Op1, + cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, Op1, byteMask, false, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; CondCodesF = CondCodesMaskF & newCpsr; - CondCodesQ = CondCodesMaskQ & newCpsr; CondCodesGE = CondCodesMaskGE & newCpsr; ''' msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", @@ -111,11 +110,10 @@ let {{ msrCpsrImmCode = ''' SCTLR sctlr = Sctlr; uint32_t newCpsr = - cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE, imm, + cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, imm, byteMask, false, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; CondCodesF = CondCodesMaskF & newCpsr; - CondCodesQ = CondCodesMaskQ & newCpsr; CondCodesGE = CondCodesMaskGE & newCpsr; ''' msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", @@ -205,9 +203,7 @@ let {{ int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); int32_t res; if (satInt(res, operand, imm)) - CondCodesQ = CondCodesQ | (1 << 27); - else - CondCodesQ = CondCodesQ; + CpsrQ = 1 << 27; Dest = res; ''' ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", @@ -221,9 +217,7 @@ let {{ int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); int32_t res; if (uSatInt(res, operand, imm)) - CondCodesQ = CondCodesQ | (1 << 27); - else - CondCodesQ = CondCodesQ; + CpsrQ = 1 << 27; Dest = res; ''' usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", @@ -236,14 +230,13 @@ let {{ ssat16Code = ''' int32_t res; uint32_t resTemp = 0; - CondCodesQ = CondCodesQ; int32_t argLow = sext<16>(bits(Op1, 15, 0)); int32_t argHigh = sext<16>(bits(Op1, 31, 16)); if (satInt(res, argLow, imm)) - CondCodesQ = CondCodesQ | (1 << 27); + CpsrQ = 1 << 27; replaceBits(resTemp, 15, 0, res); if (satInt(res, argHigh, imm)) - CondCodesQ = CondCodesQ | (1 << 27); + CpsrQ = 1 << 27; replaceBits(resTemp, 31, 16, res); Dest = resTemp; ''' @@ -257,14 +250,13 @@ let {{ usat16Code = ''' int32_t res; uint32_t resTemp = 0; - CondCodesQ = CondCodesQ; int32_t argLow = sext<16>(bits(Op1, 15, 0)); int32_t argHigh = sext<16>(bits(Op1, 31, 16)); if (uSatInt(res, argLow, imm)) - CondCodesQ = CondCodesQ | (1 << 27); + CpsrQ = 1 << 27; replaceBits(resTemp, 15, 0, res); if (uSatInt(res, argHigh, imm)) - CondCodesQ = CondCodesQ | (1 << 27); + CpsrQ = 1 << 27; replaceBits(resTemp, 31, 16, res); Dest = resTemp; ''' diff --git a/src/arch/arm/isa/insts/mult.isa b/src/arch/arm/isa/insts/mult.isa index b02386c63b..31febe7470 100644 --- a/src/arch/arm/isa/insts/mult.isa +++ b/src/arch/arm/isa/insts/mult.isa @@ -44,7 +44,7 @@ let {{ exec_output = "" calcQCode = ''' - CondCodesQ = CondCodesQ | ((resTemp & 1) << 27); + CpsrQ = (resTemp & 1) << 27; ''' calcCcCode = ''' diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 9053f6e92b..ead058b4c8 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -157,7 +157,6 @@ def operands {{ #Pseudo integer condition code registers 'CondCodesF': intRegCC('INTREG_CONDCODES_F'), - 'CondCodesQ': intRegCC('INTREG_CONDCODES_Q'), 'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'), 'OptCondCodesF': intRegCC( '''(condCode == COND_AL || condCode == COND_UC) ? @@ -219,6 +218,7 @@ def operands {{ #Fixed index control regs 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr), + 'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr), 'Spsr': cntrlRegNC('MISCREG_SPSR'), 'Fpsr': cntrlRegNC('MISCREG_FPSR'), 'Fpsid': cntrlRegNC('MISCREG_FPSID'), diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 813b98b692..7f16924f25 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -67,6 +67,7 @@ namespace ArmISA enum MiscRegIndex { MISCREG_CPSR = 0, + MISCREG_CPSR_Q, MISCREG_SPSR, MISCREG_SPSR_FIQ, MISCREG_SPSR_IRQ, @@ -209,7 +210,7 @@ namespace ArmISA unsigned crm, unsigned opc2); const char * const miscRegName[NUM_MISCREGS] = { - "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", + "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_mon", "spsr_und", "spsr_abt", "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", "mvfr0", "mvfr1", @@ -269,9 +270,9 @@ namespace ArmISA // This mask selects bits of the CPSR that actually go in the CondCodes // integer register to allow renaming. - static const uint32_t CondCodesMask = 0xF80F0000; + static const uint32_t CondCodesMask = 0xF00F0000; static const uint32_t CondCodesMaskF = 0xF0000000; - static const uint32_t CondCodesMaskQ = 0x08000000; + static const uint32_t CpsrMaskQ = 0x08000000; static const uint32_t CondCodesMaskGE = 0x000F0000; BitUnion32(SCTLR) diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc index 4fc4a0ed28..bc42f8e9d0 100644 --- a/src/arch/arm/nativetrace.cc +++ b/src/arch/arm/nativetrace.cc @@ -117,7 +117,6 @@ Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc) //CPSR newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR) | tc->readIntReg(INTREG_CONDCODES_F) | - tc->readIntReg(INTREG_CONDCODES_Q) | tc->readIntReg(INTREG_CONDCODES_GE); changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);