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dev-arm: Don't panic when EOIR a non active PPI

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GIC architecture specification says that writing EOIR with
a not active irq it is an unpredictable behavior.
So, just warn when it happens for a PPI case, like it is
already done in SPI case.

Change-Id: Icb1b8f5690d5e87b15c3b0fe2ca0d37fdd4085ee
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13556
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Adrien Pesle
2018-10-12 12:42:33 +02:00
committed by Giacomo Travaglini
parent 9181c2ea16
commit e086e74a79
1 changed files with 1 additions and 1 deletions
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2
src/dev/arm/gic_v2.cc
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@@ -601,7 +601,7 @@ GicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
} else if (iar.ack_id < (SGI_MAX + PPI_MAX) ) {
uint32_t int_num = 1 << (iar.ack_id - SGI_MAX);
if (!(cpuPpiActive[ctx] & int_num))
panic("CPU %d Done handling a PPI interrupt "
warn("CPU %d Done handling a PPI interrupt "
"that isn't active?\n", ctx);
cpuPpiActive[ctx] &= ~int_num;
} else {