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mem: Rework the structuring of the prefetchers

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Re-organizes the prefetcher class structure. Previously the
BasePrefetcher forced multiple assumptions on the prefetchers that
inherited from it. This patch makes the BasePrefetcher class truly
representative of base functionality. For example, the base class no
longer enforces FIFO order. Instead, prefetchers with FIFO requests
(like the existing stride and tagged prefetchers) now inherit from a
new QueuedPrefetcher base class.

Finally, the stride-based prefetcher now assumes a custimizable lookup table
(sets/ways) rather than the previous fully associative structure.
This commit is contained in:
Mitch Hayenga
2014-12-23 09:31:18 -05:00
parent 6cb58b2bd2
commit df82a2d003
11 changed files with 598 additions and 486 deletions
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10
src/mem/cache/cache_impl.hh vendored
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@@ -535,7 +535,7 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
bool satisfied = access(pkt, blk, lat, writebacks);
// track time of availability of next prefetch, if any
Tick next_pf_time = 0;
Tick next_pf_time = MaxTick;
bool needsResponse = pkt->needsResponse();
@@ -548,7 +548,7 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
// Don't notify on SWPrefetch
if (!pkt->cmd.isSWPrefetch())
next_pf_time = prefetcher->notify(pkt, time);
next_pf_time = prefetcher->notify(pkt);
}
if (needsResponse) {
@@ -648,7 +648,7 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
if (prefetcher) {
// Don't notify on SWPrefetch
if (!pkt->cmd.isSWPrefetch())
next_pf_time = prefetcher->notify(pkt, time);
next_pf_time = prefetcher->notify(pkt);
}
}
} else {
@@ -688,12 +688,12 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
if (prefetcher) {
// Don't notify on SWPrefetch
if (!pkt->cmd.isSWPrefetch())
next_pf_time = prefetcher->notify(pkt, time);
next_pf_time = prefetcher->notify(pkt);
}
}
}
if (next_pf_time != 0)
if (next_pf_time != MaxTick)
requestMemSideBus(Request_PF, std::max(time, next_pf_time));
// copy writebacks to write buffer