From df6a318a8646b5a9b197dfe27a3b4c36ac31741c Mon Sep 17 00:00:00 2001 From: Jason Lowe-Power Date: Fri, 1 Nov 2024 08:59:33 -0700 Subject: [PATCH] arch-x86: Update MTRR defType register (#1732) Signed-off-by: Jason Lowe-Power --- src/arch/x86/isa.cc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc index 89b4328d66..65618dc857 100644 --- a/src/arch/x86/isa.cc +++ b/src/arch/x86/isa.cc @@ -38,6 +38,7 @@ #include "cpu/base.hh" #include "cpu/thread_context.hh" #include "debug/MatRegs.hh" +#include "debug/X86.hh" #include "params/X86ISA.hh" #include "sim/serialize.hh" @@ -124,6 +125,10 @@ ISA::clear() regVal[misc_reg::Pat] = 0x0007040600070406ULL; + // Bit 11 is mttr enable (1), bit 10 is fixed range enable (1) + // bits 0-7 is default type (6, which means WB) + regVal[misc_reg::DefType] = 0xC06; + regVal[misc_reg::Syscfg] = 0x20601; regVal[misc_reg::TopMem] = 0x4000000; @@ -228,6 +233,9 @@ ISA::readMiscRegNoEffect(RegIndex idx) const RegVal ISA::readMiscReg(RegIndex idx) { + + DPRINTF(X86, "Reading misc reg %#x, value: %#llx\n", idx, regVal[idx]); + if (idx == misc_reg::Tsc) { return regVal[misc_reg::Tsc] + tc->getCpuPtr()->curCycle(); }