Split BaseCache::CacheEvent into RequestEvent and ResponseEvent.

Compiles but not tested.

--HG--
extra : convert_revision : 4e1e28c4b87721ccfcf35a5ea62c1fa324acbaf9

src/mem/cache/base_cache.hh

@@ -117,13 +117,22 @@ class BaseCache : public MemObject
         std::list<std::pair<Tick,PacketPtr> > transmitList;
     };
 
-    struct CacheEvent : public Event
+    struct RequestEvent : public Event
     {
         CachePort *cachePort;
         PacketPtr pkt;
-        bool newResponse;
 
-        CacheEvent(CachePort *_cachePort, bool response);
+        RequestEvent(CachePort *_cachePort, Tick when);
+        void process();
+        const char *description();
+    };
+
+    struct ResponseEvent : public Event
+    {
+        CachePort *cachePort;
+        PacketPtr pkt;
+
+        ResponseEvent(CachePort *_cachePort);
         void process();
         const char *description();
     };
@@ -132,8 +141,8 @@ class BaseCache : public MemObject
     CachePort *cpuSidePort;
     CachePort *memSidePort;
 
-    CacheEvent *sendEvent;
-    CacheEvent *memSendEvent;
+    ResponseEvent *sendEvent;
+    ResponseEvent *memSendEvent;
 
   private:
     void recvStatusChange(Port::Status status, bool isCpuSide)
@@ -432,9 +441,7 @@ class BaseCache : public MemObject
     {
         if (!doMasterRequest() && !memSidePort->waitingOnRetry)
         {
-            BaseCache::CacheEvent * reqCpu =
-                new BaseCache::CacheEvent(memSidePort, false);
-            reqCpu->schedule(time);
+            new RequestEvent(memSidePort, time);
         }
         uint8_t flag = 1<<cause;
         masterRequests |= flag;
@@ -469,9 +476,7 @@ class BaseCache : public MemObject
     {
         if (!doSlaveRequest() && !cpuSidePort->waitingOnRetry)
         {
-            BaseCache::CacheEvent * reqCpu =
-                new BaseCache::CacheEvent(cpuSidePort, false);
-            reqCpu->schedule(time);
+            new RequestEvent(cpuSidePort, time);
         }
         uint8_t flag = 1<<cause;
         slaveRequests |= flag;